5238-DS03-405-R datasheet(49/76 Pages) BOARDCOM

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Advance Data Sheet

BCM5238

1/31/03

Broa d c om Co rp o r a t i o n

Document

5238-DS03-405-R

Auxiliary Control/Status Register

Page 41

Jabber Disable. 10BASE-T operation only. Bit 15 of the Auxiliary Control register allows the user to disable the Jabber

Detect function, defined in the IEEE standard. This function shuts off the transmitter when a transmission request has

exceeded a maximum time limit. By writing a 1 to bit 15 of the Auxiliary Control Register, the Jabber Detect function is

disabled. Writing a 0 to this bit or resetting the chip restores normal operation. Reading this bit returns the value of Jabber

Detect Disable.

Link Disable. Writing a 1 to bit 14 of the Auxiliary Control register allows the user to disable the Link Integrity state machines,

and place the BCM5248 into forced link pass status. Writing a 0 to this bit or resetting the chip restores the Link Integrity

functions. Reading this bit returns the value of Link Integrity Disable.

HSQ:LSQ. Extends or decreases the squelch levels for detection of incoming 10BASE-T data packets. The default squelch

levels implemented are those defined in the IEEE standard. The high-squelch and low-squelch levels are useful for situations

where the IEEE-prescribed levels are inadequate. The squelch levels are used by the CRS/link block to filter out noise and

recognize only valid packet preambles and link integrity pulses. Extending the squelch levels allows the BCM5248 to operate

properly over longer cable lengths. Decreasing the squelch levels may be useful in situations where there is a high level of

noise present on the cables. Reading these two bits returns the value of the squelch levels.

Edge Rate [1:0]. Control bits used to program the transmit DAC output edge rate in 100BASE-TX mode. These bits are

logically ANDed with the ER[1:0] input pins to produce the internal edge-rate controls (Edge_Rate[1] AND ER[1],

Edge_Rate[0] AND ER[0]).

Auto-Negotiation Indicator. A read-only bit that indicates whether auto-negotiation has been enabled or disabled on the

BCM5248. A combination of a 1 in bit 12 of the Control register and a logic 1 on the ANEN input pin is required to enable

auto-negotiation. When auto-negotiation is disabled, bit 3 of the Auxiliary Control register returns a 0. At all other times, it

returns a 1.

Force100/10 Indication. A read-only bit that returns a value of 0 when one of following two cases is true:

•

The ANEN pin is low AND the F100 pin is low

•

Bit 12 of the Control register has been written as 0 AND bit 13 of the Control register has been written as 0. When bit 8

of the Auxiliary Control register is 0, the speed of the chip is 10BASE-T. In all other cases, either the speed is not forced

(auto-negotiation is enabled), or the speed is forced to 100BASE-X.

Speed Indication. Bit 1 of the Auxiliary Control register is a read-only bit that shows the true current operation speed of the

BCM5248. A 1 bit indicates 100BASE-X operation, whereas a 0 indicates 10BASE-T operation. Note that while the auto-

negotiation exchange is being performed, the BCM5248 is always operating at 10BASE-T speed.

Full-Duplex Indication. Bit 0 of the Auxiliary Control register is a read-only bit that returns a 1 when the BCM5238 is in full-

duplex mode. In all other modes, it returns a 0.

Full-Duplex Indication

1 = Full-duplex active

0 = Full-duplex not active

a. When writing to this register, preserve existing values of reserved bits by completing a Read/Modify Write.

Table 31: Auxiliary Control/Status Register (Address 24d, 18h) (Cont.)

Bit

Name

R/W

Description

DEFAULT

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

5238-DS03-405-R Datasheet(PDF) 49 Page - Broadcom Corporation.

5238-DS03-405-R Datasheet(HTML) 49 Page - Broadcom Corporation.

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