5238-DS03-405-R datasheet(13/76 Pages) BOARDCOM

13 / 76 page

Advance Data Sheet

BCM5238

1/31/03

Broa d c om Co rp o r a t i o n

Document

5238-DS03-405-R

Source Synchronous SMII (SSSMII) Interface

Page 5

Data and control signals passing from the MAC to the PHY use the serial transmit (STX) line; data and control signals

passing from the PHY to the MAC use the serial receive (SRXD) line. All bit transfers are synchronous with clock (SCLK) at

125 MHz; frame sync is provided by a fourth line (SYNC), asserted at the beginning of each frame, which occurs every ten

cycles of REF_CLK. Each PHY is provided with an STX and an SRX pair. Pins TXD0{x} and RXD0{x}, where x is the number

of the specific PHY, are used to perform the STX and SRX functions on the BCM5238.

The chip has a single SCLK and SYNC input which is common to all PHYs. Pins REF_CLK and SSYNC are used for these

functions on the BCM5238.

Receive data and control information are passed from the PHY to the MAC in ten-bit frames. In 100 Mbps mode, each frame

represents a new byte of data. In 10 Mbps mode, each byte of data is repeated ten times; the MAC can sample any one of

every ten frames. Since the timing of data coming from a remote transmitter is not synchronized with the local SCLK or SYNC

lines and may contain errors in frequency, a FIFO capable of storing 28 bits is provided in each receive path. The received

data bits and the RX_DV signal are passed through the FIFO; the CRS bit is not. It is asserted for the time the wire is

receiving a frame. If the remote transmitter is idle and no data needs to be passed from the receiver, status information

becomes available.

Transmit data and control information are passed from the MAC to the PHY in ten-bit frames, as in the receive path. In 100

megabit mode, each frame represents a new byte of data. In 10 Mbps mode, each byte of data is repeated ten times; the

PHY can transmit any one of every ten frames.

SOURCE SYNCHRONOUS SMII (SSSMII) INTERFACE

From a data signaling standpoint, the source synchronous SMII is essentially identical to standard SMII. The only difference

is that source synchronous employs specific 125 MHz clocks and SYNC signals that travel in the same direction as the data,

TXD0 and RXD0, and are synchronous to the data.

Therefore, a source synchronous capable MAC which sends TXD0 to the PHY must also send a source synchronous 125-

MHz clock and SYNC signal to the PHY. The PHY uses this clock and SYNC to latch-in and delineate the TXD0 data stream.

Similarly, the BCM5238 in source synchronous SMII mode drives RXD0 to the MAC along with a 125 MHz clock and SYNC

signals. The MAC should use this clock and SYNC to latch-in and delineate RXD0 data streams.

By using these separate clock and SYNC signals, SMII timing constraints are significantly eased.

5238-DS03-405-R Datasheet(PDF) 13 Page - Broadcom Corporation.