F280041PMSR datasheet(39/218 Pages) TI1

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TMS320F280049, TMS320F280049C

TMS320F280048, TMS320F280048C, TMS320F280045

TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C

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SPRS945C – JANUARY 2017 – REVISED DECEMBER 2017

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Terminal Configuration and Functions

4.3.3

Power and Ground

Table 4-4. Power and Ground

SIGNAL NAME

DESCRIPTION

TYPE

GPIO

100 PZ

PMQ

64 PM

56 RSH

VDD

1.2-V Digital Logic Power Pins. TI

recommends placing a decoupling capacitor

near each VDD pin with a minimum total

capacitance of approximately 20 µF. When

not using the internal voltage regulator, the

exact value of the decoupling capacitance

should be determined by your system voltage

regulation solution.

4, 46,

71, 87

27, 4,

44, 59

27, 4,

44, 59

24, 41,

5, 53

VDDA

3.3-V Analog Power Pins. Place a minimum

2.2-µF decoupling capacitor to VSSA on each

pin.

11, 34

VDDIO

3.3-V Digital I/O Power Pins. Place a

minimum 0.1-µF decoupling capacitor on each

pin.

3, 47,

70, 88

28, 43,

25, 40,

VDDIO_SW

Supply pin for the internal DC-DC regulator. If

the internal DC-DC regulator is used, a bulk

input capacitance of 20-µF should be placed

on this pin. If the internal DC-DC regulator is

not used, this pin should be treated as a

VDDIO pin.

VSS

Digital Ground

45, 5,

72, 86

26, 45,

5, 58

26, 45,

5, 58

PAD

VSSA

Analog Ground

12, 33

VSS_SW

Internal DC-DC regulator ground. If the

internal DC-DC regulator is not used, this pin

must be treated as a VSS pin.

F280041PMSR Datasheet(PDF) 39 Page - Texas Instruments

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