F280041PMSR datasheet(40/218 Pages) TI1

40 / 218 page

TMS320F280049, TMS320F280049C

TMS320F280048, TMS320F280048C, TMS320F280045

TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C

SPRS945C – JANUARY 2017 – REVISED DECEMBER 2017

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Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C TMS320F280045

TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C

Terminal Configuration and Functions

4.3.4

Test, JTAG, Voltage Regulator, and Reset

Table 4-5. Test, JTAG, Voltage Regulator, and Reset

SIGNAL NAME

DESCRIPTION

TYPE

GPIO

100 PZ

PMQ

64 PM

56 RSH

FLT1

Flash test pin 1. Reserved for TI. Must be left

unconnected.

I/O

FLT2

Flash test pin 2. Reserved for TI. Must be left

unconnected.

I/O

TCK

JTAG test clock with internal pullup.

TMS

JTAG test-mode select (TMS) with internal

pullup. This serial control input is clocked into

the TAP controller on the rising edge of TCK.

This device does not have a TRSTn pin. An

external pullup resistor (recommended 2.2

kΩ) on the TMS pin to VDDIO should be

placed on the board to keep JTAG in reset

during normal operation.

VREGENZ

Internal voltage regulator enable with internal

pulldown. Tie directly to VSS (low) to enable

the internal VREG. Tie directly to VDDIO

(high) to use an external supply.

Crystal oscillator input or single-ended clock

input. The device initialization software must

configure this pin before the crystal oscillator

is enabled. To use this oscillator, a quartz

crystal circuit must be connected to X1 and

X2. This pin can also be used to feed a

single-ended 3.3-V level clock.

I/O

XRSn

Device Reset (in) and Watchdog Reset (out).

During a power-on condition, this pin is driven

low by the device. An external circuit may also

drive this pin to assert a device reset. This pin

is also driven low by the MCU when a

watchdog reset occurs. During watchdog

reset, the XRSn pin is driven low for the

watchdog reset duration of 512 OSCCLK

cycles. A resistor with a value from 2.2 kΩ to

10 kΩ should be placed between XRSn and

VDDIO. If a capacitor is placed between

XRSn and VSS for noise filtering, it should be

100 nF or smaller. These values allow the

watchdog to properly drive the XRSn pin to

VOL within 512 OSCCLK cycles when the

watchdog reset is asserted. The output buffer

of this pin is an open-drain with an internal

pullup. If this pin is driven by an external

device, TI recommends using an open-drain

device.

I/OD

F280041PMSR Datasheet(PDF) 40 Page - Texas Instruments

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