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STA003T Datasheet(PDF) 10 Page - STMicroelectronics |
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STA003T Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 32 page  3.4 - READ OPERATION (see Fig. 10) 3.4.1 - Current byte address read The STA003T has an internal byte address counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, follow- ing a START condition the master sends the de- vice address with the RW bit set to 1. The STA003T acknowledges this and outputs the byte addressed by the internal byte address counter. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. 3.4.2 - Sequential address read This mode can be initiated with either a current address read or a random address read. How- ever in this case the master does acknowledge the data byte output and the STA003T continues to output the next byte in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte, but terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after one byte output. 4 - I 2C REGISTERS The following table gives a description of the MPEG Source Decoder (STA003T) register list. The first column (HEX_COD) is the hexadecimal code for the sub-address. The second column (DEC_COD) is the decimal code. The third column (DESCRIPTION) is the descrip- tion of the information contained in the register. The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default is "undefined". The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful size of the register itself. Each register is 8 bit wide. The master shall oper- ate reading or writing on 8 bits only. I 2C REGISTERS HEX_COD DEC_COD DESCRIPTION RESET R/W 0x00 0 VERSION R (8) 0x01 1 IDENT 0xAC R (8) 0x05 5 PLLCTL [7:0] 0x21 R/W (8) 0x06 6 PLLCTL_M 0x0C R/W (8) 0x07 7 PLLCTL_N 0x00 R/W (8) 0x0B 11 reserved 0x0C 12 reserved 0x0D 13 SCLK_POL 0x04 R/W (8) 0x0F 15 ERROR_CODE 0x00 R (8) DEV-ADDR ACK START D98AU826A RW DATA NO ACK STOP CURRENT ADDRESS READ DEV-ADDR ACK START RW SUB-ADDR ACK DEV-ADDR ACK STOP RANDOM ADDRESS READ DATA NO ACK START RW DEV-ADDR ACK START DATA ACK DATA ACK STOP SEQUENTIAL CURRENT READ DATA NO ACK DEV-ADDR ACK START RW SUB-ADDR ACK DEV-ADDR ACK SEQUENTIAL RANDOM READ DATA ACK START RW DATA ACK NO ACK STOP DATA RW= HIGH Figure 10. Read Mode Sequence STA003T 10/32 |
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