LM12434CIWM datasheet(27/80 Pages) NSC

27 / 80 page

60 Operational Information (Continued)

Acquisition Time

The LM12434 and LM12 L 438’s internal SH is designed

to operate at its minimum acquisition time (1125 15 ms

for a 12-bit a sign conversion) when the source imped-

ance RS is less than or equal to 60 80 X (fCLK s 8 6

MHz) When 60 80 X k RS s 417 556 kX the inter-

nal SH’s acquisition time can be increased to a maximum

of 488

s (12 a sign bits fCLK e 8 6 MHz) to

provide sufficient time for the sampling capacitor to charge

See Section 621 (Instruction RAM ‘‘00’’) Bits 12 – 15 for

more information

Instruction Register

The INSTRUCTION RAM is divided into 8 separate words

each with 48 (3 x 16) bit length Each word is separated into

three 16-bit sections Each word has a unique address and

different sections of the instruction word are selected by the

2-bit RAM pointer (RP) in the configuration register As

shown in

Figure 7 the Instruction RAM sections are labeled

Instructions Limits

1 and Limits

2 The Instruction sec-

tion holds operational (12-bit a sign 8-bit a sign or watch-

dog) information such as the input channels to be selected

the mode of operation to be performed for each instruction

and the duration of the acquisition period The other two

sections are used in the watchdog mode and the user-

defined limits are stored in them Each watchdog instruction

has 2 limits associated with it (usually a low limit and a high

limit but two low limits or two high limits may be pro-

grammed instead) The DAS starts executing from instruc-

tion 0 and moves through the next instructions up to any

user-specified instruction and then ‘‘loop back’’ to instruc-

tion 0 It is not necessary to execute all 8 instructions in the

instruction loop The cycle may be repeatedly executed until

stopped by the user The processor should access the In-

struction RAM only when the instruction sequencer is

stopped

FIFO Register

The FIFO Register stores the conversion results This regis-

ter is ‘‘Read only’’ and all the locations are accessed

through a single address Each time a conversion is per-

formed the result is stored in the FIFO and the FIFO’s inter-

nal write pointer points to the next location The pointer rolls

back to location 1 after a Write to location 32 The same

flow occurs when reading from the FIFO The internal FIFO

Writes and the external FIFO Reads do not affect each oth-

er’s pointer locations

Microprocessor overhead is reduced through the use of the

internal conversion FIFO Thirty-two consecutive conver-

sions can be completed and stored in the FIFO without any

microprocessor intervention The microprocessor can at

any time interrogate the FIFO and retrieve its contents It

can also wait for the LM12434 and LM12 L 438 to issue an

interrupt when the FIFO is full or after any number (s 32) of

conversions have been stored

Configuration Register

The CONFIGURATION Register is the main ‘‘control panel’’

of the DAS Writing 1s and 0s to the different bits of the

Configuration Register commands the DAS start or stop the

sequencer reset the pointers and flags go into ‘‘standby’’

mode for low power consumption calibrate offset and lin-

earity and select sections of the RAM

Other Registers

The INTERRUPT ENABLE Register lets the user activate up

to 7 sources for interrupt generation (refer to Section 623)

It also holds two user-programmable values One is the

number of conversions to be stored in the FIFO register

before the generation of the Data Ready interrupt The other

value is the instruction number that generates an interrupt

when the sequencer reaches that instruction

The INTERRUPT STATUS and LIMIT STATUS Registers

are ‘‘Read only’’ registers They are used as vectors to indi-

cate which conditions have generated the interrupt and

what watchdog limit boundaries have been passed Note

that the bits are set in the status registers upon occurrence

of their corresponding interrupt conditions regardless of

whether the condition is enabled for external interrupt gen-

eration

The TIMER Register can be programmed to insert a delay

before execution of each instruction A bit in the instruction

the execution of an instruction

Serial IO

A very flexible serial synchronous interface is provided to

facilitate reading from and writing to the LM12434 and

LM12 L 438’s registers The communication between the

LM12434 and LM12 L 438 and microcontrollers micro-

processors and other circuitry is accomplished through this

serial interface The serial interface is designed to directly

communicate with the synchronous serial interfaces of the

most popular microprocessors with no extra hardware re-

quirement The interface has been also designed to simplify

software development

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