LM12434CIWM datasheet(41/80 Pages) NSC

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70 Digital Interface

In order to read from or write to the registers of the

LM12434 and LM12 L 438 a very flexible serial synchro-

nous interface is provided Communication between the

LM12434 and LM12 L 438 and microcontrollers micro-

processors and other circuitry is accomplished through this

serial interface The serial interface is designed to directly

communicate with synchronous serial interface of the most

popular microprocessors and I2C serial protocol with no ad-

ditional hardware required The interface has been also de-

signed to accommodate easy and straightforward software

programming

The LM12434 and LM12 L 438 supports four selectable

protocols as shown in Table VI The MODESEL1 and

MODESEL2 inputs select the desired protocol These pins

are normally hardwired for a selected protocol but they can

also be controlled by the system in case a protocol change

within the system is required P1 – P5 are multi-function seri-

al interface input or output pins that have different assign-

ments depending on the selected interface mode

The ‘‘Standard’’ interface mode uses a simple shift register

type of serial data transfer It supports several microcontrol-

lers’ serial synchronous protocols including National Semi-

conductor’s MICROWIREPLUS Motorola’s SPl QSPl and

Hitachi’s synchronous SCl Section 711 shows general

block diagrams of how the serial DAS configured in the

Standard Interface Mode can be connected to the HPC and

68HC11 Also detailed assembly routines are included for

single writes single reads and burst read operations

The ‘‘8051’’ mode supports the synchronous serial interface

of the 8051 family of microcontrollers (8051 serial interface

Mode 0) It is also compatible with the serial interface in the

MCS-96 family of 16-bit microcontrollers Section 721

shows a general block diagram of how the serial DAS con-

figured in the 8051 Interface Modes can be connected to

the 8051 family of mCs Also detailed assembly routines for

a single write single read and burst read operations are

included

The ‘‘TMS320’’ mode is designed to directly interact with

the serial interface of the TMS320C3x and TMS320C5x

families of digital signal processors This interface is also

compatible with the similar serial interfaces on the

DSP56000 and the ADSP2100 families of DSP processors

Section 731 shows a general block diagram of how the

serial DAS configured in the TMS320 interface mode can

be connected to the TMS320C3x family of DSP processors

Also detailed assembly routines for a single write single

read and burst read operations are included

The ‘‘I2C’’ mode supports the Philips’ I2C bus specification

for both the standard (100 kHz maximum data rate) and the

fast (400 kHz maximum data rate) modes of operation The

DAS behaves as a slave device on the I2C bus and receives

and transmits the information under the control of a bus

master Section 741 shows a general block diagram of

how the serial DAS configured in the I2C Interface mode

can be connected to an I2C bus using an I2C controller

(PCD8584)

All the serial interface modes allow for three basic types of

data transfer these are single write single read and burst

read In a single write or read 16 bits (2 bytes) of data is

written to or read from one of the registers inside the DAS

In a burst read multiple reads are performed from one regis-

ter without having to repeatedly send the control and regis-

ter address information for each read The burst read can

be performed on any LM12434 and LM12 L 438’s register

however it is primarily provided for multiple reads from the

FlFO register (one address 32 locations) where a se-

quence of conversion results is stored

71 STANDARD INTERFACE MODE

The standard interface mode is a simple shift register type

of serial data transfer The serial clock synchronizes the

transfer of data to and from the LM12434 and LM12 L 438

The interface uses 4 lines 2 data lines (DI and DO) a serial

clock line (SCLK) and a chip-select (CS) line More than one

device can share the data and serial clock lines provided

that each device has its own chip-select line

The LM12434 and LM12 L 438 standard mode is selected

when the MODESEL1 and MODESEL2 pins have the logic

state of ‘‘01’’

Figure 12 shows a typical connection diagram

for the LM12434 and LM12 L 438 standard mode serial

interface The CS DI DO and SCLK lines are respectively

assigned to interface pins P2 through P5 The P1 pin is

assigned to a signal called RF (RiseFall) The logic level

on this pin specifies the polarity of the serial clock

If RF e 1 data is shifted after falling edge and is stable

and captured at the rising edge of the SCLK

If RF e 0 data is shifted after rising edge and is stable

and captured at the falling edge of the SCLK

TABLE VI LM12434 and LM12 L 438 Interface Modes and Pin Assignments

Interface

M0DESEL1

MODESEL2

Mode

Standard

R F

SCLK

8051

RXD

TXD

TMS320

FSR

FSX

CLK

I2C

Slave AD0

Slave AD1

Slave AD2

SDA

SCL

Internally pulled-up

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