LM12434CIWM datasheet(56/80 Pages) NSC

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70 Digital Interface (Continued)

Burst read cycle

A burst read cycle starts the same way

as a single read cycle but the B bit in the command byte is

set to one indicating a burst read cycle Following the com-

mand byte the data is output on the RXD line as long as the

DAS receives TXD clock from the system To tell the DAS

when a burst read cycle is completed CS should be set high

after the 8th and before the 15th SCLK cycle during the last

data byte transfer (see

Figure 13c ) After CS high is detect-

ed and the last data bit is transferred the DAS is ready for a

new communication cycle to begin

The timing diagrams in

Figure 13 show the transfer of data

in packets of 8 bits (bytes) This represents the way the

serial ports of the 8051 family of microcontrollers produce

the serial clock and data The DAS does not require a gap

between

the

first

and

second

bytes

the

data

16 continuous clock cycles will transfer the data word How-

ever there should be a gap equal to 3 CLK (the DAS main

clock input not the TXD clock) cycles between the end of

the command byte and the start of the data during a read

cycle This is not concerned in most systems for two rea-

sons First the processor generally has some inherent gap

between byte transfers Second the TXD frequency is usu-

ally significantly slower than the CLK frequency For exam-

ple an 8051 processor with 12 MHz crystal generates a

TXD of 1 MHz If the DAS is running with 6 MHz CLK there

are 6 cycles of CLK within each cycle of TXD and the re-

quirement is satisfied even if TXD comes continuously after

command byte The user should pay attention to this re-

quirement if running the TXD with a speed near or higher

than CLK

TLH11879 – 40

(a) Write Cycle

Idle State of SCLK e 1 Data Shifted at the Rising Edge of the SCLK

TLH11879 – 41

(b) Read Cycle

Idle State of SCLK e 1 Data Shifted at the Rising Edge of the SCLK

FIGURE 13 Timing Diagrams for LM12434 and LM12 L 438 8051 Serial Interface Mode

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