ACT8849 datasheet(32/35 Pages) ACTIVE-SEMI

32 / 35 page

ACT8849

Rev PrB, 12-Jun-14

Innovative PowerTM

- 32 -

www.active-semi.com

Active-Semi Confidential―Do Not Copy or Distribute

ActivePMU

TM is a trademark of Active-Semi.

I2CTM is a trademark of NXP.

Enable / Disable Control

During normal operation, each buck may be enabled

or disabled via the I2C interface by writing to that

regulator's ON[ ] bit.

OK[ ] and Output Fault Interrupt

Each DC/DC features a power-OK status bit that can

be read by the system microprocessor via the I2C

interface. If an output voltage is lower than the power-

OK threshold, typically 7% below the programmed

regulation voltage, that regulator's OK[ ] bit will be 0.

If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8849

will interrupt the processor if that DC/DC's output

voltage falls below the power-OK threshold. In this

case, nIRQ will assert low and remain asserted until

either the regulator is turned off or back in regulation,

and the OK[ ] bit has been read via I2C.

PCB Layout Considerations

High switching frequencies and large peak currents

make PC board layout an important part of step-down

DC/DC converter design. A good design minimizes

excessive EMI on the feedback paths and voltage

gradients in the ground plane, both of which can

result in instability or regulation errors.

Step-down DC/DCs exhibit discontinuous input

current, so the input capacitors should be placed as

close as possible to the IC, and avoiding the use of

via if possible. The inductor, input filter capacitor, and

output filter capacitor should be connected as close

together as possible, with short, direct, and wide

traces. The ground nodes for each regulator's power

loop should be connected at a single point in a star-

ground configuration, and this point should be

connected to the backside ground plane with multiple

via. The output node for each regulator should be

connected to its corresponding OUTx pin through the

shortest possible route, while keeping sufficient

distance from switching nodes to prevent noise

injection. Finally, the exposed pad should be directly

connected to the backside ground plane using

multiple via to achieve low electrical and thermal

resistance.

REGx/VSET[2:0]

000

001

010

011

100

101

110

111

000

0.600

0.800

1.000

1.200

1.600

2.000

2.400

3.200

001

0.625

0.825

1.025

1.250

1.650

2.050

2.500

3.300

010

0.650

0.850

1.050

1.300

1.700

2.100

2.600

3.400

011

0.675

0.875

1.075

1.350

1.750

2.150

2.700

3.500

100

0.700

0.900

1.100

1.400

1.800

2.200

2.800

3.600

101

0.725

0.925

1.125

1.450

1.850

2.250

2.900

3.700

110

0.750

0.950

1.150

1.500

1.900

2.300

3.000

3.800

111

0.775

0.975

1.175

1.550

1.950

2.350

3.100

3.900

REGx/VSET[5:3]

Table 3:

REGx/VSET[ ] Output Voltage Setting

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