Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

MP8845CGC Datasheet(PDF) 5 Page - Monolithic Power Systems

Part # MP8845CGC
Description  5A High Efficient Synchronous Step-Down Switchers with I2C Interface
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8845CGC Datasheet(HTML) 5 Page - Monolithic Power Systems

  MP8845CGC Datasheet HTML 1Page - Monolithic Power Systems MP8845CGC Datasheet HTML 2Page - Monolithic Power Systems MP8845CGC Datasheet HTML 3Page - Monolithic Power Systems MP8845CGC Datasheet HTML 4Page - Monolithic Power Systems MP8845CGC Datasheet HTML 5Page - Monolithic Power Systems MP8845CGC Datasheet HTML 6Page - Monolithic Power Systems MP8845CGC Datasheet HTML 7Page - Monolithic Power Systems MP8845CGC Datasheet HTML 8Page - Monolithic Power Systems MP8845CGC Datasheet HTML 9Page - Monolithic Power Systems Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 20 page
background image
MP8845C – 5A HIGH EFFICIENT SYNC. STEP DOWN SWITCHER WITH I2C
MP8845C Rev. 1.02
www.MonolithicPower.com
5
4/25/2014
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
I/O LEVEL CHARACTERISTICS
(continued)
Parameter
Symbol
Condition
HS-Mode
LS-Mode
Units
Min
Max
Min
Max
Fall time of SDAH signal
tfDA
Capacitive load from
10pF to 100pF
10
80
-
-
ns
Capacitive load of
400pF
20
160
20
250
ns
Pulse width of spikes that
must be suppressed by
the input filter
tSP
0
10
0
50
ns
Input current each I/O pin
Ii
Input voltage between
0.1Vcc and 0.9Vcc
-
10
-10
+10
uA
Capacitance for each I/O
pin
Ci
-
10
-
10
pF
I2C PORT SIGNAL CHARACTERISTICS
Parameter
Symbol
Condition
Cb=100pF
Cb=400pF
Units
Min
Max
Min
Max
SCLH and SCL clock
frequency
fSCHL
0
3.4
0
0.4
MHz
Set-up time for a
repeated START
condition
TSU;STA
160
-
600
-
ns
Hold time (repeated)
START condition
THD;STA
160
-
600
-
ns
Low period of the SCL
clock
tLOW
160
-
1300
-
ns
High period of the SCL
clock
tHIGH
60
-
600
-
ns
Data set-up time
TSU:DAT
10
-
100
-
ns
Data hold time
THD;DAT
0
70
0
-
ns
Rise time of SCLH signal
trCL
10
40
20*0.1Cb
300
ns
Rise time of SCLH signal
after a repeated START
condition and after an
acknowledge bit
tfCL1
10
80
20*0.1Cb
300
ns
Fall time of SCLH signal
TfCL
10
40
20*0.1Cb
300
ns
Rise time of SDAH signal
tfDA
10
80
20*0.1Cb
300
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com