UT7Q512 datasheet(2/16 Pages) AEROFLEX

2 / 16 page

PIN NAMES

DEVICE OPERATION

The UT7Q512 has three control inputs called Enable 1 ( E), Write

Enable ( W), and Output Enable (G); 19 address inputs, A(18:0);

and eight bidirectional data lines, DQ(7:0).The E Device Enable

controls device selection, active, and standby modes. Asserting

E enables the device, causes IDD to rise to its active value, and

decodes the 19 address inputs to select one of 524,288 words in

the memory. W controls read and write operations. During a

read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of W greater than V

IH (min) , G and E less than

VIL (max) defines a read cycle. Read access time is measured

from the latter ofDeviceEnable, Output Enable, or valid address

to valid data output.

SRAM read Cycle 1, the Address Access in figure 3a, is initiated

by a change in address inputs while the chip is enabled with G

asserted and W deasserted. Valid data appears on data outputs

DQ(7:0) after the specified tAVQV is satisfied. Outputs remain

active throughout the entire cycle. As long as Device Enable and

Output Enable are active, the address inputs may change at a

rate equal to the minimum read cycle time (t

AVAV).

SRAM read Cycle 2, the Chip Enable-Controlled Access in

figure 3b, is initiated by E going active while G remains asserted,

W remains deasserted, and the addresses remain stable for the

entire cycle. After the specified tETQV is satisfied, the eight-bit

word addressed by A(18:0) is accessed and appears at the data

outputs DQ(7:0).

SRAM read Cycle 3, the Output Enable-Controlled Access in

figure 3c, is initiated by G going active while E is asserted, W

is deasserted, and the addresses are stable. Read access time is

tGLQV unless tAVQV or tETQV have not been satisfied.

A(18:0)

Address

DQ(7:0)

Data Input/Output

Chip Enable

Write Enable

Output Enable

VDD

Power

VSS

Ground

Figure 2a. UT7Q512 100ns SRAM Shielded

Package Pinout (36)

A15

A17

A13

A11

VSS

VDD

A10

DQ7

DQ6

DQ5

DQ4

A18

A16

A14

A12

VDD

VSS

DQ0

DQ1

DQ2

DQ3

Figure 2b. UT7Q512 100ns SRAM

Package Pinout (32)

VDD

A15

A17

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

A18

A16

A14

A12

DQ0

DQ1

DQ2

VSS

I/O Mode

Mode

3-state

Standby

Data in

Write

3-state

Data out

Read

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