AD6636BBCZ1 datasheet(55/72 Pages) AD

55 / 72 page

AD6636

Rev. 0 | Page 55 of 72

Table 29. Memory Map

8-Bit Hex

Address

Byte 3

Byte 2

Byte 1

Byte 0

8-Bit Hex

Address

0x03

Open <7:6>, Channel

Enable <5:0>

Open<7:6>, Channel I/O

Access Control<5:0>

Chip I/O Access Control

<7:0> (default 0x00)

Open<7:0>

0x00

0x07

Open <15:11>, LVDS Control<10:0> (default 0x06FC)

Soft Synchronization

Configuration<7:0>

Pin Synchronization

Configuration<7:0>

0x04

0x0B

Interrupt Mask <15:0>

Interrupt Status <15:0> (read only, default 0x00)

0x08

ADC Input Port Register Map—Addresses 0x0C to 0x67

0x0F

ADC Input Control <31:0>

0x0C

0x13

Open<15:0>

ADC CLK Control <15:0> (default 0x0000)

0x10

0x17

Port AB, IQ Correction Control<15:0> (default 0x0000)

Port CD, IQ Correction Control <15:0> (default 0x0000)

0x14

0x1B

Port AB, DC Offset Correction I<15:0>

Port AB, DC Offset Correction Q<15:0>

0x18

0x1F

Port CD, DC Offset Correction I<15:0>

Port CD, DC Offset Correction Q<15:0>

0x1B

0x23

Port AB, Phase Offset Correction <15:0>

Port AB, Amplitude Offset Correction <15:0>

0x20

0x27

Port CD, Phase Offset Correction <15:0>

Port CD, Amplitude Offset Correction <15:0>

0x24

0x2B

Port A Gain Control <7:0>

Open<23:20>, Port A Dwell Timer <19:0>

0x28

0x2F

Open<7:0>

Port A Power Monitor Period <23:0>

0x2C

0x33

Open<7:5>, Port A Signal

Monitor<4:0>

Port A Power Monitor Output <23:0>

0x30

0x37

Open<15:10>, Port A Lower Threshold <9:0>

Open <15:10>, Port A Upper Threshold <9:0>

0x34

0x3B

Port B Gain Control <7:0>

Open<23:20>, Port B Dwell Timer <19:0>

0x38

0x3F

Open<7:0>

Port B Power Monitor Period <23:0>

0x3C

0x43

Open<7:5>, Port B Signal

Monitor<4:0>

Port B Power Monitor Output <23:0>

0x40

0x47

Open<15:10>, Port B Lower Threshold <9:0>

Open <15:10>, Port B Upper Threshold <9:0>

0x44

0x4B

Port C Gain Control <7:0>

Open<23:20>, Port C Dwell Timer <19:0>

0x48

0x4F

Open<7:0>

Port C Power Monitor Period <23:0>

0x4C

0x53

Open<7:5>, Port C Signal

Monitor<4:0>

Port C Power Monitor Output <23:0>

0x50

0x57

Open<15:10>, Port C Lower Threshold <9:0>

Open <15:10>, Port C Upper Threshold <9:0>

0x54

0x5B

Port D Gain Control <7:0>

Open<23:20>, Port D Dwell Timer <19:0>

0x58

0x5F

Open<7:0>

Port D Power Monitor Period <23:0>

0x5C

0x63

Open<7:5>, Port D Signal

Monitor<4:0>

Port D Power Monitor Output <23:0>

0x60

0x67

Open<15:10>, Port D Lower Threshold <9:0>

Open <15:10>, Port D Upper Threshold <9:0>

0x64

Channel Register Map—Addresses 0x68 to 0xBB

0x6B

Open<15:0>

Open<15:9>, NCO Control<8:0>

0x68

0x6F

NCO Start Hold-Off Counter<15:0>

NCO Frequency Hold-Off Counter<15:0>

0x6C

0x73

NCO Frequency <31:0> (default 0x0000 0000)

0x70

0x77

Open<15:0>

NCO Phase Offset<15:0> (default 0x0000)

0x74

0x7B

Open<7:1>, CIC

Bypass<0>

Open<7:5>, CIC

Decimation<4:0>

Open<7:5>, CIC Scale

Factor<4:0>

Open<7:4>, FIR-HB

Control<3:0>

0x78

0x7F

Open<15:0>

Open<15:13>, MRCF Control<12:0>

0x7C

0x83

Open<7:6>, MRCF

Coefficient 3 <5:0>

Open<7:6>, MRCF

Coefficient 2 <5:0>

Open<7:6>, MRCF

Coefficient 1 <5:0>

Open<7:6>, MRCF

Coefficient 0 <5:0>

0x80

0x87

Open<7:6>, MRCF

Coefficient 7 <5:0>

Open<7:6>, MRCF

Coefficient 6 <5:0>

Open<7:6>, MRCF

Coefficient 5 <5:0>

Open<7:6>, MRCF

Coefficient 4 <5:0>

0x84

0x8B

Open<15:13>, DRCF Control Register<12:0>

Open <7:6>, DRCF

Coefficient Offset<5:0>

Open<7>, DRCF Taps

<6:0>

0x88

0x8F

Open<15:0>

Open <7:6>, DRCF Final

Address<5:0>

Open <7:6>, DRCF Start

Address<5:0>

0x8C

0x93

Open<15:0>

Open<15:14>, DRCF Coefficient Memory <13:0>

0x90

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