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LTM4646

4646f

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PIN FUNCTIONS

CPWR (F8): Input Power to the Control IC, and Power

to the DRVCC Regulator. This pin is connected to VIN for

normal 4.5V to 20V operation. For lower voltage inputs

below 4.5V, CPWR can be powered with an external 5V

bias. See Application section.

COMP1A, COMP2A (G3, E3): Current Control Threshold.

These pins are the output of the error amplifier and the

switching regulator’s compensation point. The current

comparator threshold increases with this control voltage.

The voltage ranges from 0V to 2.4V.

COMP1B, COMP2B (G1, E1): Internal Compensation

Network .These pins are to be connected to their respected

COMPA pins. When Utilizing specific external compensa-

tion, then float these pins.

MODE_PLLIN (F3): Operation Mode Selection or External

Clock Synchronization Input. When this pin is tied to INTVCC,

forced continuous mode operation is selected. Tying this pin

to SGND allows discontinuous mode operation. When an

external clock is applied at this pin, both channels operate

in forced continuous mode and synchronize to the external

clock. This pin has an internal 600k pull-down resistor to

SGND. An external clock applied to MODE_PLLIN should

be within ±30% of this programmed frequency to ensure

frequency lock.

CLKOUT (F4): Clock output with phase control using the

PHASMD pin to enable multiphase operation between

devices. Its output level swings between INTVCC and SGND.

If clock input is present at the MODE_PLLIN pin, it will

be synchronized to the input clock, with phase set by the

PHASMD pin. If no clock is present at MODE_PLLIN, its

frequency will be set by the FREQ pin. To synchronize other

controllers, it can be connected to their MODE_PLLIN pins.

See the Applications Information section.

RUN1, RUN2 (H5, D5): Run Control Pins. A voltage above

1.3V will turn on each channel in the module. A voltage below

1.0V on the RUN pin will turn off the related channel. Each

RUN pin has a 1.2A pull-up current, once the RUN pin

reaches 1.2V an additional 4.5A pull-up current is added

to this pin. A 100k resistor to ground is internal, and can be

used with a pull-up resistor to VIN toturnonthemoduleusing

the external and internal resistor to program under voltage

lockout. Otherwise, an external enable signal or source can

drive these pins directly below the 6V max. Enabling either

RUN pin will turn on the DRVCC, and turn on the INTVCCpath

for operation. See Figure1 and Applications section.

PHASMD (H2): Connect this pin to SGND, INTVCC, or

floating this pin to select the phase of CLKOUT and chan-

nel 2. See Electrical Characteristics table and Application

section.

PGOOD1, PGOOD2 (G5, E5): Output Voltage Power Good

Indicator. Open-drain logic output that is pulled to ground

when the output voltage is not within ±7.5% of the regula-

tion point. See Applications section.

INTVCC (F6): Supply Input for Internal Circuitry (Not

Including Gate Drivers). This bias is derived from DRVCC

internally.

EXTVCC (E7): External Power Input. When EXTVCC exceeds

the switchover voltage (typically 4.6V), an internal switch

connects this pin to DRVCC and shuts down the internal

regulator so that INTVCC and gate drivers draw power

from EXTVCC. The VIN pin still needs to be powered up

but draws minimum current.

TEMP1+,TEMP1– and TEMP2+, TEMP2– (L8, K8 and

B8, A8): Onboard temperature diode for monitoring each

channel with differential connections for noise immunity.

VIN1 (K4-K5, L4-L5) and VIN2 (A4-A5, B4-B5): Power

Input Pins. Apply input voltage between these pins and

GND pins. Recommend placing input decoupling capaci-

tance directly between VIN pins and GND pins.

VOUTS1– (J3): Differential Output Sense Amplifier (–) Input

of channel 1. Connect this pin to the negative terminal of

the output load capacitor of VOUT1.

VOUTS2– (D4): Differential Output Sense Amplifier (–)

Input of channel 2. Connect this pin to the negative ter-

minal of the output load capacitor of VOUT2.

SW1 (H8, J8) and SW2 (C8, D8): Switching node of each

channel that is used for testing purposes. Also an R-C

snubber network can be applied to reduce or eliminate

switch node ringing, or otherwise leave floating. See the

Applications Information section.

VRNG (D2): Current Limit Adjustment Range. Tying this

pin to INTVCC sets full 10A current, or tying to SGND will

lower the current limit to 5A. Default to INTVCC.

(Recommended to Use Test Points to Monitor Signal Pin Connections.)

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