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LTC7812

7812fc

For more information www.linear.com/LTC7812

APPLICATIONS INFORMATION

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for the LTC7812 is approximately

95ns for the buck and 120ns for the boost. However, as

the peak sense voltage decreases the minimum on-time

gradually increases up to about 130ns. This is of particu-

lar concern in forced continuous applications with low

ripple current at light loads. If the duty cycle drops below

the minimum on-time limit in this situation, a significant

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC7812 circuits: 1) IC VBIAS current, 2) INTVCC

regulator current, 3) I2R losses, 4) Topside MOSFET

transition losses.

1. The VBIAS current is the DC supply current given in the

Electrical Characteristics table, which excludes MOS-

FET driver and control currents. VBIAS current typically

results in a small (<0.1%) loss.

2. INTVCC current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

from INTVCCto ground. The resulting dQ/dt is a current

out of INTVCC that is typically much larger than the

control circuit current. In continuous mode, IGATECHG

= f(QT + QB), where QT and QB are the gate charges of

the topside and bottom side MOSFETs.

SupplyingINTVCCfromanoutput-derivedsourcepower

through EXTVCC will scale the VIN current required for

thedriverandcontrolcircuitsbyafactorof(DutyCycle)/

(Efficiency). For example, in a 20V to 5V application,

10mAofINTVCCcurrentresultsinapproximately2.5mA

of VIN current. This reduces the mid-current loss from

10% or more (if the driver was powered directly from

VIN) to only a few percent.

3. I2R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current flows through L and

RSENSE, but is “chopped” between the topside MOSFET

andthesynchronousMOSFET.IfthetwoMOSFETshave

approximately the same RDS(ON), then the resistance

of one MOSFET can simply be summed with the resis-

tances of L, RSENSE and ESR to obtain I2R losses. For

example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE

= 10mΩ and RESR = 40mΩ (sum of both input and

output capacitance losses), then the total resistance

is 130mΩ. This results in losses ranging from 3% to

13% as the output current increases from 1A to 5A for

a 5V output, or a 4% to 20% loss for a 3.3V output.

Efficiency varies as the inverse square of VOUT for the

same external components and output power level. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

4. Transition losses apply only to the top MOSFET(s) (bot-

tomMOSFETfortheboost),andbecomesignificantonly

when operating at high input voltages (typically 15V or

greater). Transition losses can be estimated from:

Transition Loss = (1.7)VIN2 • IO(MAX) • CRSS • f

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efficiency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

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