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LTC2321-16

232116fc

For more information www.linear.com/2321-16

2.5V

OVDD

LTC2321-16

FPGA OR DSP

232116 F22

SDO2+

SDO2–

SCK+

SCK–

CLKOUT+

CLKOUT–

SDO1+

SDO1–

CNV

CMOS/LVDS

–

100

–

100

–

100

–

100

applicaTions inForMaTion

Figure 22. LTC2321 Using the LVDS Interface

DIGITAL INTERFACE

The LTC2321-16 features a serial digital interface that

is simple and straight forward to use. The flexible OVDD

supply allows the LTC2321-16 to communicate with any

digital logic operating between 1.8V and 2.5V. A 64MHz

external clock must be applied at the SCK pin to achieve

2Msps throughput.

In addition to a standard CMOS SPI interface, the

LTC2321-16 provides an optional LVDS SPI interface to

support low noise digital design. The CMOS/LVDS pin is

used to select the digital interface mode.

The falling edge of SCK outputs the conversion result MSB

first on the SDO pins. CLKOUT provides a skew-matched

clock to latch the SDO output at the receiver. The timing

skew of the CLKOUT and SDO outputs are matched. For

high throughput applications, using CLKOUT instead of

SCK to capture the SDO output eases timing requirements

at the receiver.

In CMOS mode, use the SDO1+, SDO2+ and CLKOUT+

pins as outputs. Use the SCK+ pin as an input. Do not

connect the SDO1–, SDO2–, SCK– and CLKOUT– pins,

as they each have internal pull-down circuitry to OGND.

In LVDS mode, use the SDO1+/SDO1–, SDO2+/SDO2– and

CLKOUT+/CLKOUT– pins as differential outputs. These

pins must be differentially terminated by an external 100Ω

resistor at the receiver (FPGA). The SCK+/SCK– pins are

differential inputs and must be terminated differentially by

an external 100Ω resistor at the receiver (ADC).

BOARD LAYOUT

To obtain the best performance from the LTC2321-16,

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals adjacent to analog signals or underneath

the ADC.

Recommended Layout

The following is an example of a recommended PCB lay-

out. A single solid ground plane is used. Bypass capaci-

tors to the supplies are placed as close as possible to the

supply pins. Low impedance common returns for these

bypass capacitors are essential to the low noise opera-

tion of the ADC. The analog input traces are screened by

ground. For more details and information, refer to the

DC1996, the evaluation kit for the LTC2321-16.

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