HIP4086, HIP4086A

FN4220 Rev 1.00

Page 12 of 17

January 12, 2017

Typical Application Circuit

Figure 23 is an example of how the HIP4086 and HIP4086A

3-phase drivers can be applied to drive a 3-phase motor.

Depending on the application, the switching speed of the bridge

FETs can be reduced by adding series connected resistors

between the xHO outputs and the FET gates. Gate-to-source

resistors are recommended on the low-side FETs to prevent

unexpected turn-on of the bridge should the bridge voltage be

FETs are not usually required if low-side gate-to-source resistors

are used. If relatively small gate-to-source resistors are used on

the high-side FETs, be aware that they will load the charge pump

of the HIP4086 negating the ability of the charge pump to keep

the high-side driver biased during very long periods.

An important operating condition that is frequently overlooked by

designers is the negative transient on the xHS pins that occurs

when the high-side bridge FET turns off. The absolute maximum

transient allowed on the xHS pin is -6V but it is wise to minimize

the amplitude to lower levels. This transient is the result of the

parasitic inductance of the low-side drain-to-source conductor on

the PCB. Even the parasitic inductance of the low-side FET

contributes to this transient.

When the high-side bridge FET turns off, because of the inductive

characteristics of a motor load, the current that was flowing in

the high-side FET (blue) must rapidly commutate to flow through

the low-side FET (red). The amplitude of the negative transient

impressed on the xHS node is (di/dt x L) where L is the total

parasitic inductance of the low-side FET drain-to-source path and

di/dt is the rate at which the high-side FET is turned off. With the

increasing power levels of new generation motor drives,

clamping this transient becomes more and more significant for

the proper operation of the HIP4086/A.

There are several ways of reducing the amplitude of this

transient. If the bridge FETs are turned off more slowly to reduce

di/dt, the amplitude will be reduced but at the expense of more

switching losses in the FETs. Careful PCB design will also reduce

the value of the parasitic inductance. However, these two

solutions by themselves may not be sufficient. Figure 24

illustrates a simple method for clamping the negative transient.

Two series connected, fast PN junction, 1A diodes are connected

between xHS and VSS as shown. It is important that the

components be placed as close as possible to the xHS and VSS

pins to minimize the parasitic inductance of this current path.

Two series connected diodes are required because they are in

parallel with the body diode of the low-side FET. If only one diode

is used for the clamp, it will conduct some of the negative load

current that is flowing in the low-side FET. In severe cases, a

small value resistor in series with the xHS pin as shown, will

further reduce the amplitude of the negative transient.

Please note that a similar transient with a positive polarity occurs

when the low-side FET turns off. This is less frequently a problem

because xHS node is floating up toward the bridge bias voltage.

The absolute maximum voltage rating for the xHS node does

need to be observed when the positive transient occurs.

Controller

AHO

CLO

BLO

ALO

CHO

BHO

CLI

BLI

ALI

CHI

BHI

AHI

CHS

AHS

BHS

CHB

AHB

BHB

VDD

RDEL

VDD

Speed

Brake

Battery

24V...48V

VSS

FIGURE 23. TYPICAL APPLICATION CIRCUIT

FIGURE 24. BRIDGE WITH PARASITIC INDUCTANCES

VSS

xH S

xL O

xH O

IN D UCT IV E

LO A D

+

-

+

-