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HIP2121 Datasheet(PDF) 14 Page - Renesas Technology Corp |
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HIP2121 Datasheet(HTML) 14 Page - Renesas Technology Corp |
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14 / 16 page ![]() FN7668 Rev 0.00 Page 14 of 16 December 23, 2011 HIP2120, HIP2121 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2011. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. EPAD Design Considerations The thermal pad of the HIP2120/21 is electrically isolated. It’s primary function is to provide heat sinking for the IC. It is recommended to tie the EPAD to VSS (GND). Figure 24 is an example of how to use vias to remove heat from the IC substrate. Depending on the amount of power dissipated by the HIP2120/21, it may be necessary, to connect the EPAD to one or more ground plane layers. A via array, within the area of the EPAD, will conduct heat from the EPAD to the gnd plane on the bottom layer. If inner PCB layers are available, it is also be desireable to connect these additional layers with the plated-through vias. The number of vias and the size of the GND planes required for adequate heatsinking is determined by the power dissipated by the HIP2120/21, the air flow, and the maximum temperature of the air around the IC. It is important that the vias have a low thermal resistance for efficient heat transfer. Do not use “thermal relief” patterns to connect the vias. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: HIP2120, HIP2121 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php FIGURE 24. PCB VIA PATTERN EPAD GND PLANE COMPONENT LAYER EPAD GND PLANE BOTTOM LAYER FIGURE 24. TYPICAL PCB PATTERN FOR THERMAL VIAS Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE December 23, 2011 FN7668.0 Initial Release |
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