ISL6207

FN9075 Rev 8.00

Page 7 of 10

December 2, 2005

The next larger standard value capacitance is 0.22

F. A good

quality ceramic capacitor is recommended.

Power Dissipation

Package power dissipation is mainly a function of the switching

frequency and total gate charge of the selected MOSFETs.

Calculating the power dissipation in the driver for a desired

application is critical to ensuring safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of 125°C. The maximum allowable IC power

dissipation for the SO-8 package is approximately 800mW.

When designing the driver into an application, it is

recommended that the following calculation be performed to

ensure safe operation at the desired frequency for the selected

MOSFETs. The power dissipated by the driver is approximated

as:

MOSFET selection and any external capacitance added to the

driver and is typically negligible.

Layout Considerations

Reducing Phase Ring

The parasitic inductances of the PCB and power devices (both

upper and lower FETs) could cause increased PHASE ringing,

which may lead to voltages that exceed the absolute maximum

rating of the devices. When PHASE rings below ground, the

negative voltage could add charge to the bootstrap capacitor

through the internal bootstrap diode. Under worst-case

conditions, the added charge could overstress the BOOT and/or

PHASE pins. To prevent this from happening, the user should

perform a careful layout inspection to reduce trace inductances,

and DPAK packaged MOSFETs have high parasitic lead

inductances, as opposed to SOIC-8. If higher inductance

MOSFETs must be used, a Schottky diode is recommended

across the lower MOSFET to clamp negative PHASE ring.

A good layout would help reduce the ringing on the phase and

gate nodes significantly:

• Avoid using vias for decoupling components where possible,

especially in the BOOT-to-PHASE path. Little or no use of

vias for VCC and GND is also recommended. Decoupling

loops should be short.

• All power traces (UGATE, PHASE, LGATE, GND, VCC)

should be short and wide, and avoid using vias. If vias must

be used, two or more vias per layer transition is

recommended.

• Keep the SOURCE of the upper FET as close as thermally

possible to the DRAIN of the lower FET.

• Keep the connection in between the SOURCE of lower FET

and power ground wide and short.

• Input capacitors should be placed as close to the DRAIN of

the upper FET and the SOURCE of the lower FET as

thermally possible.

Note: Refer to Intersil Tech Brief TB447 for more information.

0.0

0.4

0.1

0.2

0.3

0.5

0.6

0.7

0.8

0.9

1.0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

50nC

20nC

+

 I

+

=

FREQUENCY (kHz)

FIGURE 3. POWER DISSIPATION vs FREQUENCY

0800

200 400 600

1000 1200 1400 1600 1800 2000

1000

900

800

700

600

500

400

300

200

100

0