ISL6521 datasheet(8/14 Pages) RENESAS

8 / 14 page

ISL6521

FN9148 Rev 2.00

Page 8 of 14

Feb 8, 2005

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

(internal to the ISL6521) and the impedance networks ZIN and

ZFB. The goal of the compensation network is to provide a

closed loop transfer function with high 0dB crossing frequency

(f0dB) and adequate phase margin. Phase margin is the

difference between the closed loop phase at f0dB and 180

degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 5. Use these guidelines for

locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)

3. Place 2ND Zero at Filter’s Double Pole

4. Place 1ST Pole at the ESR Zero

5. Place 2ND Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Compensation Break Frequency Equations

Figure 6 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown in Figure 5. Using the above guidelines

should yield a Compensation Gain similar to the curve plotted.

The open loop error amplifier gain bounds the compensation

gain. Check the compensation gain at FP2 with the capabilities

of the error amplifier. The Closed Loop Gain is constructed on

the log-log graph of Figure 6 by adding the Modulator Gain (in

dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the compensation

transfer function and plotting the gain.

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

Individual Output Disable

The PWM and linear controllers can independently be

shutdown.

To disable the switching regulator, use an open-drain or open-

collector device capable of pulling the OCSET pin (with the

attached ROCSET pull-up) below 1.25V. To minimize the

possibility of OC trips at levels different than predicted, a

COCSET capacitor with a value of an order of magnitude larger

than the output capacitance of the pull-down device, has to be

FLC



LO CO



----------------------------------------

FESR

 ESR C



-----------------------------------------

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

VOUT

OSC

0.8V

ESR

VIN

VOSC

ERROR

AMP

PWM

DRIVER1

(PARASITIC)

ZFB

0.8V

RS1

COMP

VOUT

ZFB

ISL6521

ZIN

COMP

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

VE/A

ZIN

RP1

SYNC

FZ1

 R

 2C1



-----------------------------------

FZ2



RS1 R3

 C3



----------------------------------------------------------

FP1

 R

C1 C2



C1 C2

----------------------







-------------------------------------------------------

FP2

 R

 3C3



-----------------------------------

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

100

-20

-40

-60

FP1

FZ2

10M

100K

10K

100

OPEN LOOP

ERROR AMP GAIN

FZ1

FP2

FLC

FESR

COMPENSATION

FREQUENCY (Hz)

GAIN

MODULATOR

GAIN

CLOSED LOOP

GAIN

VIN

VPP

------------







log

RS1

-------------







log

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