HC55130IMZ datasheet(20/36 Pages) RENESAS

20 / 36 page

HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

FN4659 Rev 13.00

Page 20 of 36

June 1, 2006

SPM Pin

For optimum performance, the PC board interconnect the

SPM pin should be as short as possible. If pulses metering is

not being used, then this pin should be grounded as close to

the device pin as possible.

RLIM Pin

The current limiting resistor RLIM needs to be as close to the

RLIM pin as possible.

Layout of the 2-Wire Impedance Matching

Resistor ZT

Proper connection to the ZT pin is to have the external ZT

network as close to the device pin as possible.

The ZT pin is a high impedance pin that is used to set the

proper feedback for matching the impedance of the 2-wire

side. This will eliminate circuit board capacitance on this pin

to maintain the 2-wire return loss across frequency.

Digital Logic Inputs

Table 1 is the logic truth table for the 3V to 5V logic input

pins. A combination of the control pins C3, C2 and C1 select

1 of the possible 6 operating states. The 8th state listed is

Thermal Shutdown. Thermal Shutdown protection is invoked

if a fault condition on the tip or ring causes the junction

temperature of the die to exceed 175°C. A description of

each operating state and the control logic follows:

Open Circuit State (C3 = 0, C2 = 0, C1 = 0)

In this state, the tip and ring outputs are in a high impedance

condition (>1M

). No supervisory functions are available

and SHD and GKD outputs are at a TTL high level.

4-wire loopback testing can be performed in this state. With

the PTG pin floating, the signal on the VTX output is 180o out

of phase and approximately 2 times the VRX input signal. If

the PTG pin is grounded, then the amplitude will be

approximately the same as its input and 180o out of phase.

Ringing State (C3 = 0, C2 = 0, C1 = 1)

In this state, the output of the ring relay driver pin (RRLY)

goes low (energizing the ring relay to connect the ringing

signal to the phone) if either of the following two conditions

are satisfied:

(1) The RSYNC_REV pin is grounded through a resistor -

This connection enables the RRLY pin to go low the instant

the ringing state is invoked, without any regard for the

ringing voltage (90VRMS -120VRMS) across the relay

contacts. The resistor (34.8k

 to 70k) is required to limit

the current into the RSYNC_REV pin.

(2) A ring sync pulse is applied to the RSYNC_REV pin -

This connection enables the RRLY pin to go low at the

command of a ring sync pulse. A ring sync pulse should go

TABLE 1. DETECTOR STATES

STATE

SLIC OPERATING STATE

ACTIVE DETECTOR

OUTPUT

SHD

GKD_ LVM

Open Circuit State

4 wire loopback test capability

HIGH

Ringing State

(Previous State cannot be Reverse

Active State)

Ring Trip Detector

HIGH

Forward Active State

Loop Current Detector

Ground Key Detector

Test Active State

Requires previous state to be in the

Forward Active state to determine the

On hook or Off hook status of the line.

On Hook Loopback Detector

LOW

Ground Key Detector

HIGH

Off Hook Loop Current Detector

LOW

Line Voltage Detector

Tip Open - Ground Start State

Ground Key Detector

Reserved

N/A

Reverse Active State

Loop Current Detector

Ground Key Detector

Test Reversal Active State

Requires previous state to be in the

Reverse Active state to determine the

On hook or Off hook status of the line.

On Hook Loop Current Detector

HIGH

Off Hook Loop Current Detector

LOW

Line Voltage Detector

Thermal Shutdown

LOW

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