ICL7650S

FN2920 Rev 10.00

Page 3 of 13

April 12, 2007

Absolute Maximum Ratings

Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +0.3) to (V- -0.3)

Voltage on Oscillator Control Pins . . . . . . . . . . . . . . . . . . . . V+ to V-

Duration of Output Short Circuit. . . . . . . . . . . . . . . . . . . . . Indefinite

Current to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

While Operating (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .100

A

Operating Conditions

Temperature Range

ICL7650SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Thermal Resistance (Typical, Note 2)

8 Lead PDIP Package* . . . . . . . . . . . .

110

N/A

14 Lead PDIP Package . . . . . . . . . . . .

90

N/A

8 Lead SOIC Package . . . . . . . . . . . . .

160

N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . .. -55°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing applications.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Limiting input current to 100

A is recommended to avoid latchup problems. Typically 1mA is safe, however this is not guaranteed.

2.

Electrical Specifications

PARAMETER

SYMBOL

TEST CONDITIONS

TEMP.

(°C)

MIN

TYP

MAX

UNITS

Input Offset Voltage

(Note 3)

+25

-

0.7

5

V

0 to +70

-

1

8

V

Average Temperature Coefficient of

Input Offset Voltage

(Note 3)

0 to +70

-

0.02

-

V/°C

Change in Input Offset with Time

+25

-

100

-

nV/

month

Input Bias Current

|I(+)|, |I(-)|

+25

-

4

10

pA

0 to +70

-

520

pA

Input Offset Current

|I(-), |I(+)|

+25

-

820

pA

0 to +70

-

10

40

pA

Input Resistance

+25

-

-



Large Signal Voltage Gain

(Note 3)

+25

135

150

-dB

0 to +70

130

--

dB

Output Voltage Swing (Note 4)

+25

4.7

4.85

-

V

+25

-

4.95

-

V

Common Mode Voltage Range

(Note 3)

CMVR

+25

-5

-5.2 to +4

3.5

V

0 to +70

-5

-

3.5

V

Common Mode Rejection Ratio

(Note 3)

CMRR

CMVR = -5V to +3.5V

+25

120

140

-dB

0 to +70

120

--

dB

Power Supply Rejection Ratio

PSRR

+25

120

140

-dB

Input Noise Voltage

f = DC to 10Hz

+25

-

2

-

Input Noise Current

f = 10Hz

+25

-

0.01

-

pA/

Hz

Gain Bandwidth Product

GBWP

+25

-

2

-

MHz

Slew Rate

SR

+25

-

2.5

-

V/

s

Rise Time

+25

-

0.2

-

s

Overshoot

OS

+25

-

20

-

%

Operating Supply Range

V+ to V-

+25

4.5

-

16

V

Supply Current

No Load

+25

-

2

3

mA

0 to +70

-

-

3.2

mA