SGM708-RYS8GSLASHTR datasheet(9/13 Pages) SGMICRO

9 / 13 page

Low-Cost, Microprocessor

SGM708

Supervisory Circuit

DECEMBER 2017

SG Micro Corp

www.sg-micro.com

APPLICATION INFORMATION

Ensuring a Valid RESET Output Down to

VCC = 0V

When VCC falls below 1V, the SGM708 RESET output

no longer sinks current-it becomes an open circuit.

High-impedance CMOS logic inputs can drift to

undetermined voltages if left undriven. If a pull-down

resistor is added to the RESET pin as shown in Figure

1, any stray charge or leakage currents will be drained

to ground, holding RESET low. Resistor value (R1) is

not critical. It should be about 100kΩ, large enough not

to load RESET and small enough to pull RESET to

ground.

SGM708

RESET

Figure 1. RESET Valid to Ground Circuit

Monitoring Voltages Other Than the

Unregulated DC Input

Monitor voltages other than the unregulated DC by

connecting a voltage divider to PFI and adjusting the

ratio appropriately. If required, add hysteresis by

connecting a resistor (with a value approximately 10

times the sum of the two resistors in the potential

divider network) between PFI and PFO . A capacitor

between PFI and GND will reduce the power-fail

circuit’s sensitivity to high-frequency noise on the line

being monitored. RESET can be asserted on other

voltages in addition to the +5V VCC line. Connect PFO

to MR to initiate a RESET pulse when PFI drops

below 1.25V. Figure 2 shows the SGM708 configured

to assert RESET when the +5V supply falls below the

reset threshold, or when the +12V supply falls below

approximately 11V.

VCC

PFO

PFI

RESET

+12V +5V

1MΩ

130kΩ

TO μP

GND

SGM708

Figure 2. Monitoring Both +5V and +12V

Monitoring a Negative Voltage

The power-fail comparator can also monitor a negative

supply rail (Figure 3). When the negative rail is good (a

negative voltage of large magnitude), PFO is low, and

when the negative rail is degraded (a negative voltage

of lesser magnitude), PFO is high. By adding the

resistors and transistor as shown, a high PFO triggers

reset. As long as PFO remains high, the SGM708 will

keep reset asserted (RESET = low, RESET = high).

Note that this circuit’s accuracy depends on the PFI

threshold tolerance, the VCC line, and the resistors.

VCC

PFO

PFI

+5V

GND

SGM708

V-

100k

μP

+5V

V-

VTRIP

PFO

– 1.25

1.25 - VTRIP

VTRIP < 0

2N3904

RESET

Figure 3. Monitoring a Negative Voltage

Interfacing to μPs with Bidirectional Reset

Pins

μPs with bidirectional reset pins, such as the Motorola

68HC11 series, can contend with the SGM708 RESET

output. If, for example, the RESET output is driven high

and the Microprocessor wants to pull it low,

indeterminate logic levels may result. To correct this,

connect a 4.7kΩ resistor between the RESET output

and the μP reset I/O, as in Figure 4. Buffer the RESET

output to other system components.

VCC

RESET

Microprocessor

GND

SGM708

VCC

RESET

GND

4.7kΩ

BUFFRED RESET TO OTHER SYSTEM COMPONENTS

Figure 4. Interfacing to Microprocessors with

Bidirectional Reset I/O

SGM708-RYS8G/TR Datasheet(PDF) 9 Page - SG Micro Corp

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