ZL2103ALAF datasheet(23/28 Pages) RENESAS

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ZL2103

FN6966 Rev 5.00

Page 23 of 28

May 3, 2011

the user may also configure a specific ramp rate using the SS

pin. Tracking mode is enabled through the CFG pin, as shown in

Table 16, and configured through the SS pin, as shown in

Table 13.

Any device that is configured for tracking mode will ignore its

soft-start delay and ramp time settings (SS pin) and its output

will take on the turn-on/turn-off characteristics of the reference

voltage present at the VTRK pin. All of the ENABLE pins in the

tracking group must be connected together and driven by a

single logic source.

Tracking mode can also be configured via the I2C/SMBus

interface by using the TRACK_CONFIG PMBus command. Please

refer to Application Note AN2033 for more information on

configuring tracking mode using PMBus.

Voltage Margining

The ZL2103 offers a simple means to vary its output higher or

lower than its nominal voltage setting in order to determine

whether the load device is capable of operating over its specified

supply voltage range. The MGN command is set by driving the

MGN pin or through the I2C/SMBus interface. The MGN pin is a

tri-level input that is continuously monitored and can be driven

directly by a processor I/O pin or other logic-level output.

The ZL2103’s output will be forced higher than its nominal set

point when the MGN command is set HIGH, and the output will

be forced lower than its nominal set point when the MGN

command is set LOW. Default margin limits of VNOM ±5% are pre-

loaded in the factory, but the margin limits can be modified

through the I2C/SMBus interface to as high as VNOM + 10% or as

low as 0V, where VNOM is the nominal output voltage set point

determined by the VSET pin. A safety feature prevents the user

from configuring the output voltage to exceed VNOM + 10% under

any conditions.

The margin limits and the MGN command can both be set

individually through the I2C/SMBus interface. Additionally, the

transition rate between the nominal output voltage and either

margin limit can be configured through the I2C/SMBus interface.

Please refer to Application Note AN2033 for detailed instructions

on modifying the margining configurations.

TABLE 13. TRACKING MODE CONFIGURATION

RSS

)

UVLO

(V)

TRACKING RATIO

(%)

UPPER TRACK LIMIT

RAMP-UP/DOWN BEHAVIOR

19.6

5.5

100

Limited by target voltage

Output not allowed to decrease before PG

21.5

Output will always follow VTRK

23.7

Limited by VTRK pin voltage

Output not allowed to decrease before PG

26.1

Output will always follow VTRK

28.7

Limited by target voltage

Output not allowed to decrease before PG

31.6

Output will always follow VTRK

34.8

Limited by VTRK pin voltage

Output not allowed to decrease before PG

38.3

Output will always follow VTRK

56.2

7.5

100

Limited by target voltage

Output not allowed to decrease before PG

61.9

Output will always follow VTRK

68.1

Limited by VTRK pin voltage

Output not allowed to decrease before PG

Output will always follow VTRK

82.5

Limited by target voltage

Output not allowed to decrease before PG

90.9

Output will always follow VTRK

100

Limited by VTRK pin voltage

Output not allowed to decrease before PG

110

Output will always follow VTRK

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