HT46C47 datasheet(16/39 Pages) HOLTEK

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HT46R47/HT46C47

Rev. 1.30

May 3, 2004

A/D Converter

The 4 channels and 9-bit resolution A/D (8-bit accuracy)

converter are implemented in this microcontroller. The

reference voltage is VDD. The A/D converter contains 4

special registers which are; ADRL (20H), ADRH (21H),

ADCR (22H) and ACSR (23H). The ADRH and ADRL

are A/D result register higher-order byte and

lower-order byte and are read-only. After the A/D con-

version is completed, the ADRH and ADRL should be

read to get the conversion result data. The ADCR is an

A/D converter control register, which defines the A/D

channel number, analog channel select, start A/D con-

version control bit and the end of A/D conversion flag. If

the users want to start an A/D conversion, define PB

configuration, select the converted analog channel, and

give START bit a raising edge and a falling edge

®1®0). At the end of A/D conversion, the EOCB bit is

cleared and an A/D converter interrupt occurs (if the A/D

converter interrupt is enabled). The ACSR is A/D clock

setting register, which is used to select the A/D clock

source.

The A/D converter control register is used to control the

A/D converter. The bit2~bit0 of the ADCR are used to

select an analog input channel. There are a total of four

channels to select. The bit5~bit3 of the ADCR are used

to set PB configurations. PB can be an analog input or

as digital I/O line decided by these 3 bits. Once a PB line

is selected as an analog input, the I/O functions and

pull-high resistor of this I/O line are disabled, and the

A/D converter circuit is power on. The EOCB bit (bit6 of

the ADCR) is end of A/D conversion flag. Check this bit

to know when A/D conversion is completed. The START

bit of the ADCR is used to begin the conversion of A/D

converter. Give START bit a raising edge and falling

edge that means the A/D conversion has started. In or-

der to ensure the A/D conversion is completed, the

START should stay at

²0² until the EOCB is cleared to

²0² (end of A/D conversion).

The bit 7 of the ACSR is used for testing purpose only. It

can not be used for the users. The bit1 and bit0 of the

ACSR are used to select A/D clock sources.

When the A/D conversion is completed, the A/D inter-

rupt request flag is set. The EOCB bit is set to

²1² when

the START bit is set from

²0² to ²1².

ADRL

¾¾¾¾¾¾¾

ADRH

Note:

D0~D8 is A/D conversion result data bit

LSB~MSB.

Label (ADCR)

Bits

Function

ACS0

ACS1

ACS2

ACS2, ACS1, ACS0: Select A/D channel

0, 0, 0: AN0

0, 0, 1: AN1

0, 1, 0: AN2

0, 1, 1: AN3

1, X, X: undefined, cannot be used

PCR0

PCR1

PCR2

PCR2, PCR1, PCR0: PB3~PB0 configurations

0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce power consumption.)

0, 0, 1: PB3 PB2 PB1 AN0

0, 1, 0: PB3 PB2 AN1 AN0

0, 1, 1: PB3 AN2 AN1 AN0

1, x, x: AN3 AN2 AN1 AN0

EOCB

End of A/D conversion flag.

(0: end of A/D conversion)

START

Start the A/D conversion

®1®0= Start

®1= Reset A/D converter and set EOCB to ²1²

ADCR Register

Label (ACSR)

Bits

Function

ADCS0

ADCS1

Select the A/D converter clock source.

0, 0: fSYS/2

0, 1: fSYS/8

1, 0: fSYS/32

1, 1: Undefined, cannot be used.

2~6

Unused bit, read as

²0².

TEST

For internal test only.

ACSR Register

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