LVCMOS/

LVTTL OUT

IN +

IN -

8

DSLVDS1002

SNLS619 – JULY 2018

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9 Detailed Description

9.1 Overview

The DSLVDS1002 is a single channel, low voltage differential signaling (LVDS) line receiver. It operates from a

single power supply that is nominally 3.3-V, but can be as low as 3.0-V and as high as 3.6-V. The input to the

DSLVDS1002 is a differential signal complying with the LVDS Standard (TIA/EIA-644) and the output is a 3.3-V

LVCMOS/LVTTL signal. The differential input signal operates with a signal level of 340 mV, nominally, at

common-mode voltage of 1.2-V. The differential nature of the inputs provides immunity to common-mode

coupled signals that the driven signal may experience. A termination resistor of 100-Ω should be selected to

match the media, and should be located as close to the receiver as possible.

9.2 Functional Block Diagram

9.3 Feature Description

The DSLVDS1002 is capable of detecting signals as low as 100-mV, over a ±1-V common-mode range centered

around 1.2-V. The AC parameters of the input pins are optimized for a recommended operating input voltage

range of 0-V to 2.4-V (measured from each pin to ground). The device will operate for receiver input voltages up

9.4 Device Functional Modes

9.4.1 Termination

Use a termination resistor which best matches the differential impedance or your transmission line. The resistor

should be between 90

Ω and 130Ω. Remember that the current mode outputs need the termination resistor to

generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single

resistor across the pair at the receiver end will suffice.

Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the

termination to the receiver inputs should be minimized. The distance between the termination resistor and the

receiver should be < 10mm (12mm MAX).

9.4.2 Threshold

The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100mV for the LVDS receiver.

The DSLVDS1002 supports an enhanced threshold region of

−100mV to 0V. This is useful for fail-safe biasing.

The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 4. The typical DSLVDS1002 LVDS

receiver switches at about

fail-safe bias of +25mV applied, the typical differential noise margin is now the difference from the switch point to

the bias point. In the example below, this would be 55mV of Differential Noise Margin (DNM) (+25mV

−

(

−30mV)). With the enhanced threshold region of −100mV to 0V, this small external fail-safe biasing of +25mV

(with respect to 0V) gives a DNM of a comfortable 55mV. With the standard threshold region of ±100mV, the

external fail-safe biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of 155mV

which is stronger fail-safe biasing than is necessary for the DSLVDS1002. If more DNM is required, then a

stronger fail-safe bias point can be set by changing resistor values.

Figure 3. VTC of the DSLVDS1002 LVDS Receiver