9

DSLVDS1002

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SNLS619 – JULY 2018

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Device Functional Modes (continued)

9.4.3 Fail-Safe Feature

The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to

LVCMOS/LVTTL logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to

prevent noise from appearing as a valid signal.

The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe

protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.

1. Open Input Pins. It is not required to tie the receiver inputs to ground or any supply voltage. Internal failsafe

circuitry will ensure a HIGH, stable output state for open inputs.

2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a power-off condition,

the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across

the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable

picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch.

To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be

used. Twisted pair cable will offer better balance than flat ribbon cable.

3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V

differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not

supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs

shorted and no external common-mode voltage applied.

External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the

presence of higher noise levels. The pull up and pull down resistors should be in the 5k

Ω to 15kΩ range to

minimize loading and waveform distortion to the driver. The common-mode bias point should be set to

approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry.

The DSLVDS1002 is compliant to the original ANSI EIA/TIA-644 specification and is also compliant to the new

10 receivers are used.

Additional information on fail-safe biasing of LVDS devices may be found in AN-1194 Failsafe Biasing of LVDS

Interfaces (SNLA051).

9.4.4 Probing LVDS Transmission Lines

Always use high impedance (> 100k

Ω), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)

scope. Improper probing will give deceiving results.