EP Blue

VCC

GND

DSLVDS1002

Receiver

Driver

LVCMOS/LVTTL OUT

IN +

IN -

DSLVDS1001

LVCMOS/

LVTTL OUT

IN +

IN -

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to

change without notice.

DSLVDS1002

SNLS619 – JULY 2018

DSLVDS1002 3.3-V LVDS Single Channel High Speed Differential Receiver

1

1 Features

1

•

Designed for Signaling Rates up to 400-Mbps

•

Single 3.3V Power Supply Design (3.0-V to 3.6-V

Range)

•

100-ps Typical Differential Skew

•

3.5-ns Maximum Propagation Delay

•

Accepts Small Swing (±350-mV Typical)

Differential Signal Levels

•

Power Off Protection (High Impedance on LVDS

Inputs)

•

Flow-Through Pinout Simplifies PCB Layout

•

Low Power Dissipation (10 mW typical@ 3.3 V

static)

•

LVDS Receiver Inputs Accept

LVDS/BLVDS/LVPECL Inputs

•

Failsafe Protection for Open, Short and

Terminated Inputs

•

SOT-23 5-lead package

•

Meets or Exceeds ANSI TIA/EIA-644-A Standard

•

Industrial temperature operating range (

−40°C to

+85°C)

2 Applications

•

Board to Board Communication

•

Test and Measurement

•

Motor Drive

•

Wireless Infrastructure

•

Telecom Infrastructure

•

Printer

•

Multi Function Printer

•

Professional Video Cameras

•

Enterprise and Cinema Projectors

•

LED Video Wall

•

NIC Card

•

Rack Server

•

Ultrasound Scanners

3 Description

The DSLVDS1002 is a single channel Low Voltage

Differential Signaling (LVDS) receiver designed for

applications requiring low power dissipation, low

noise and high data rates. In addition, the short circuit

fault current is also minimized. The DSLVDS1002

device is designed to support data rates that are at

least 400 Mbps (200 MHz) utilizing LVDS technology.

The DSLVDS1002 accepts low voltage (±350-mV

typical) differential input signals and outputs a 3.3-V

CMOS/TTL signal. The receivers also support open,

shorted, and terminated (100

Ω) input fail-safe. The

receiver

output

will

be

HIGH

for

all

fail-safe

conditions. The DSLVDS1002 is in a 5-lead SOT-23

package that is designed for easy PCB layout.

The DSLVDS1002 can be paired with its companion

single line driver, DSLVDS1001, or with any LVDS

driver, to provide a high-speed LVDS Interference.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

DSLVDS1002

SOT-23 DBV

3.00 mm x 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Functional Block Diagram

Typical Application