MP8770

– 17V, 8A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP8770 Rev. 1.0

www.MonolithicPower.com

15

1/4/2018

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© 2018 MPS. All Rights Reserved.

Light-load operation is also called skip mode

because the HS-FET does not turn on as

frequently

as

it

does

during

heavy-load

conditions. The HS-FET turn-on frequency is a

function of the output current. As the output

current

increases,

the

current

modulator

regulation time period becomes shorter, and the

HS-FET turns on more frequently. The switching

frequency increases in turn. The output current

reaches the critical level when the current

modulator time is zero and can be determined

with Equation (1):

IN

OUT

OUT

OUT

SW

IN

(V

V

) V

I

2 L F

V





 



(1)

The device reverts to PWM mode once the

output

current

exceeds

the

critical

level.

Afterward, the switching frequency remains fairly

constant over the output current range.

VCC Regulator

The 3.5V internal regulator power most of the

exceeds 3.5V, the output of the regulator is in full

decoupling ceramic capacitor is needed at VCC.

Enable (EN)

EN is a digital control pin that turns the regulator

on and off. Drive EN above 1.1V to turn on the

regulator. Drive EN below 1V to turn off the

regulator. When floating, EN is pulled down to

GND by an internal 3.3M

Ω resistor. EN can be

input range.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP8770 UVLO comparator monitors the

output voltage of the internal regulator (VCC).

The VCC UVLO rising threshold is about 2.7V

and its falling threshold is 2.35V.

When the input voltage is higher than the UVLO

rising threshold voltage, the MP8770 powers up.

The MP8770 shuts off when the input voltage is

lower than the UVLO falling threshold voltage.

This is a non-latch protection.

Soft Start (SS)

The

MP8770

employs

a

soft

start

(SS)

mechanism to ensure smooth output ramping

during power up. When EN goes high, an

internal current source (6

μA) charges up the SS

capacitor. The SS capacitor voltage takes over

the REF voltage to the PWM comparator. The

output voltage ramps up smoothly with the SS

soft start finishes, and the device enters steady

state operation.

The SS capacitor value can be determined with

Equation (2):



ss

ss

REF

T (ms) I (uA)

C (nF)

0.83

V

(V)

(2)

If the SS cap is smaller than 4.7nF, an internal,

default, SS time (about 1.4ms) is active.

If the output capacitance is large, it is not

recommended to set the SS time too short.

Otherwise, the current limit can be reached

easily during SS.

Power Good (PG) Indicator

PG is the open drain of a MOSFET that connects

to VCC or another voltage source through a

resistor (e.g.: 100k

Ω). The MOSFET turns on

with the application of an input voltage, so PG is

5

is pulled low.

When UVLO or OTP occurs, PG is pulled low

immediately.

When

an

over-current

(OC)

When an over-voltage (OV) condition occurs, PG

If the input supply fails to power the MP8770, PG

is clamped low, even though PG is tied to an

external DC source through a pull-up resistor.

The relationship between the PG voltage and the

pull-up current is shown in Figure 5.