CYW20719 datasheet(13/49 Pages) CYPRESS

13 / 49 page

Document Number: 002-14815 Rev. *D

Page 13 of 49

PRELIMINARY

CYW20719

6.10 Serial Peripheral Interface block

The CYW20719 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations as well

as MIPI DBI-C Interface.Either of the interface can be a master/slave. SPI2 can support only one Slave. SPI1 has a 1024 byte transmit

and receive buffers which is shared with the host UART interface. SPI2 has a dedicated 256 byte transmit and receive buffers. To

support more flexibility for user applications, the CYW20719 has optional I/O ports that can be configured individually and separately

for each functional pin. SPI I/O voltage depends on VDDO.

6.10.1 MIPI interface

There are three options in DBI type-C corresponding to 9-bit, 16-bit, and 8-bit modes. The CYW20719 plays the role of host, and only

the 9-bit and 8-bit modes (option 1 and option 3 in DBI-C spec) are supported. In the 9-bit mode, the SCL, CS, MOSI, and MISO pins

are used. In the 8-bit mode, an additional pin DCX, indicating whether the current outgoing bit stream is a command or data byte is

required.

6.11 Pulse Density Modulation (PDM) Microphone

The CYW20719 accepts a ΣΔ-based one-bit PDM input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates.

The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input

shares the filter path with the aux ADC. Two types of data rates can be supported:

■ 8 kHz

■ 16 kHz

The external digital microphone takes in a 2.4 MHz clock generated by the CYW20719 and outputs a PDM signal which is registered

by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The

design can accommodate two simultaneous PDM input channels, so stereo voice is possible.

Note: Subject to the driver support in WICED Studio.

6.12 I2S Interface

The CYW20719 supports a single I2S digital audio port in both master and slave modes. The I2S signals are:

■ I2S Clock: I2S SCK

■ I2S Word Select: I2S WS

■ I2S Data Out: I2S DO

■ I2S Data In: I2S DI

I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output and I2S DI

stays as input. The channel word length is fixed to 16 bits (frame length of 32 bits) and the data is justified so that the MSB of the left-

channel data is aligned with the MSB of the I2S bus, as per I2S Specifications. The MSB of each data word is transmitted one bit clock

cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted when I2S WS is low,

and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW20719 are synchronized with the falling edge

of I2S SCK and should be sampled by the receiver on the rising edge of the I2S SCK.

The I2S port is primarily used to transfer audio samples while using the A2DP profile1. The A2DP controller is half duplex and the

direction of the audio samples depend on the A2DP role (sink/source). The I2S clock in the master mode can either be

■ 44.1 KHz x 32 bits per frame = 1411.2 KHz

■ 48 KHz x 32 bits per frame = 1536 KHz

In the slave mode, any clock rate is supported up to a maximum of 3.072 MHz.

Note: PCM interface shares HW with the I2S interface which means that both voice and audio cannot be routed at the same time.

1. The I2S port cannot be used at the application level for purposes other than routing A2DP audio samples.

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