LPC84X datasheet(2/97 Pages) NXP

2 / 97 page

LPC84x

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Product data sheet

Rev. 1.7 — 27 February 2018

2 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller



Supports In-System Programming (ISP) through USART, SPI, and I2C.



FAIM API.



FRO API.



On-chip ROM APIs for integer divide.



Digital peripherals:



High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 54

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and digital filter. GPIO direction

control supports independent set/clear/toggle of individual bits.



High-current source output driver (20 mA) on four pins.



High-current sink driver (20 mA) on two true open-drain pins.



GPIO interrupt generation capability with boolean pattern-matching feature on eight

GPIO inputs.



Switch matrix for flexible configuration of each I/O pin function.



CRC engine.



DMA with 25 channels and 13 trigger inputs.



Capacitive Touch Interface.



Timers:



One SCTimer/PWM with five input and seven output functions (including capture

and match) for timing and PWM applications. Inputs and outputs can be routed to

or from external pins and internally to or from selected peripherals. Internally, the

SCTimer/PWM supports 8 match/captures, 8 events, and 8 states.



One 32-bit general purpose counter/timer, with four match outputs and three

capture inputs. Supports PWM mode, external count, and DMA.



Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.



Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a

low-power, low-frequency internal oscillator, or an external clock input in the

always-on power domain.



Windowed Watchdog timer (WWDT).



Analog peripherals:



One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports

two independent conversion sequences.



Comparator with five input pins and external or internal reference voltage.



Two 10-bit DACs.



Serial peripherals:



Five USART interfaces with pin functions assigned through the switch matrix and

two fractional baud rate generators.



Two SPI controllers with pin functions assigned through the switch matrix.



Four I2C-bus interfaces. One I2C supports Fast-mode Plus with 1 Mbit/s data rates

on two true open-drain pins and listen mode. Three I2Cs support data rates up to

400 kbit/s on standard digital pins.



Clock generation:

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