WM8946 datasheet(39/173 Pages) CIRRUS

39 / 173 page

WM8946

Rev 4.5

SIGNAL ENHANCEMENT REGISTER CONTROLS

The SE1 ‘enable’ bits are described in Table 13. Note that other control fields must also be

determined and written to the WM8946 using WISCE™ or other tools. The registers described below

only allow the sub-blocks of SE1 to be enabled or disabled.

Note that it is not recommended to access these control fields unless appropriate values have been

written to the associated bits in registers R65 to R98.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R65 (41h)

SE1_LHPF_C

ONFIG

SE1_LHPF_R_E

SE1 Right channel low-pass / high-

pass filter enable

0 = Disabled

1 = Enabled

SE1_LHPF_L_E

SE1 Left channel low-pass / high-

pass filter enable

0 = Disabled

1 = Enabled

R68 (44h)

SE1_3D_CON

FIG

SE1_3D_R_ENA

SE1 Right channel 3D stereo

enhancement filter enable

0 = Disabled

1 = Enabled

SE1_3D_L_ENA

SE1 Left channel 3D stereo

enhancement filter enable

0 = Disabled

1 = Enabled

R71 (47h)

SE1_NOTCH_

CONFIG

SE1_NOTCH_R

_ENA

SE1 Right channel notch filters

enable

0 = Disabled

1 = Enabled

SE1_NOTCH_L_

ENA

SE1 Left channel notch filters

enable

0 = Disabled

1 = Enabled

R92 (5Ch)

SE1_DF1_CO

NFIG

SE1_DF1_R_EN

SE1 Right channel DF1 filter enable

0 = Disabled

1 = Enabled

SE1_DF1_L_EN

SE1 Left channel DF1 filter enable

0 = Disabled

1 = Enabled

Table 13 Signal Enhancement Block 1 (SE1)

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