WM8946 datasheet(21/173 Pages) CIRRUS

21 / 173 page

WM8946

Rev 4.5

(input)

SCLK

(input)

SDA

(input)

tCSU

tCHO

tSCH

tSCL

tSCY

tDHO

tDSU

Figure 8 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle)

Note: The data is latched on the 32nd falling edge of SCLK after 32 bits have been clocked into the device.

SCLK

(input)

SDOUT

(output)

tDL

(input)

Figure 9 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle)

Test Conditions

DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,

TA = +25

oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

¯¯ falling edge to SCLK rising edge

tCSU

SCLK falling edge to CS rising edge

tCHO

SCLK pulse cycle time

tSCY

200

SCLK pulse width low

tSCL

SCLK pulse width high

tSCH

SDA to SCLK set-up time

tDSU

SDA to SCLK hold time

tDHO

Pulse width of spikes that will be suppressed

tps

SCLK falling edge to SDOUT transition

tDL

WM8946 Datasheet(PDF) 21 Page - Cirrus Logic

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