LOW SKEW, 1-TO-4 LVCMOS/LVTTL

FANOUT BUFFER

8304 DATA SHEET

4

REVISION H 11/19/15

DD

= 3.3V±5%, V

DDO

DD

= V

DDO

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

IH

Input High Voltage

2

V

DD

+ 0.3

V

V

IL

Input Low Voltage

-0.3

1.3

V

I

IH

Input High Current

V

DD

= V

IN

= 3.465V

150

µA

I

IL

Input Low Current

V

DD

= 3.465V, V

IN

= 0V

-5

µA

V

OH

Output High Voltage; NOTE 1

2.1

V

V

OL

Output Low Voltage; NOTE 1

0.5

V

NOTE 1: Outputs terminated with 50

Ω

to V

DDO

/2. See Parameter Measurement Section,

“3.3V/2.5V Output Load Test Circuit”.

DD

= 3.3V±5%, V

DDO

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Maximum Output Frequency

200

MHz

tp

LH

Propagation Delay, Low-to-High;

NOTE 1

ƒ

≤ 166MHz

2.0

3.3

ns

166MHz < f

≤ 189.5MHz

2.0

3.4

ns

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

125MHz, Integration Range:

12kHz – 20MHz

0.173

ps

tsk(o)

Output Skew; NOTE 2, 4

ƒ = 133MHz

45

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

500

ps

t

R

Output Rise Time

30% to 70%

250

500

ps

t

F

Output Fall Time

30% to 70%

250

500

ps

odc

Output Duty Cycle

f

≤ 189.5MHz

40

60

%

All parameters measured at f

MAX

unless noted otherwise.

NOTE 1: Measured from V

DD

/2 of the input to V

DDO

/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V

DDO

/2.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at V

DDO

/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Maximum Output Frequency

189.5

MHz

tp

LH

Propagation Delay, Low-to-High; NOTE 1

ƒ

≤ 166MHz

2.3

3.7

ns

166MHz < f

≤ 189.5MHz

2.15

3.55

ns

tsk(o)

Output Skew; NOTE 2, 4

ƒ = 133MHz

60

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

500

ps

t

R

Output Rise Time

30% to 70%

250

500

ps

t

F

Output Fall Time

30% to 70%

250

500

ps

odc

Output Duty Cycle

f

≤ 189.5MHz

40

60

%

For NOTES, please see above Table 4A.