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8304AMLF Datasheet(PDF) 5 Page - Integrated Device Technology

Part # 8304AMLF
Description  Low Skew, 1-to-4 LVCMOS/LVTTL Fanout Buffer
PDF  11 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

8304AMLF Datasheet(HTML) 5 Page - Integrated Device Technology

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REVISION H 11/19/15
8304 DATA SHEET
5
LOW SKEW, 1-TO-4 LVCMOS/LVTTL
FANOUT BUFFER
ADDITIVE PHASE JITTER
Additive Phase Jitter @ 125MHz
(12kHz to 20MHz) = 0.173ps typical
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz
band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
As with most timing specifications, phase noise measurements has
issues.The primary issue relates to the limitations of the equipment.
Often the noise floor of the equipment is higher than the noise floor
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
of the device. This is illustrated above. The device meets the noise
floor of what is shown, but can actually be lower. The phase noise
is dependant on the input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)



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