RSC4128 datasheet(12/49 Pages) ETC

12 / 49 page

RSC-4128

Data Sheet

P/N 80-0206-J

Mapping of logical addresses 080H-0BFH (“bank” register FC is used)

Physical RAM memory

Physical memory

00H

00-3FH

08H

200-23FH

01H

40-7FH

09H

240-27FH

02H

80-BFH

0AH

280-2BFH

03H

C0-FFH

0BH

2C0-2FFH

04H

100-13FH

0CH

--- (unimplemented)

05H

140-17FH

0DH

--- (unimplemented)

06H

180-1BFH

0EH

--- (unimplemented)

07H

1C0-1FFH

0FH

--- (unimplemented)

NOTE: If a value other than those indicated above is used for the “bank” register, an undefined state will result.

See the “Special Functions Registers Summary” for details on the contents of SFRs.

L1 Vector Accelerator/Multiplier

A variety of macros are provided by Sensory that manipulate the L1 Vector Accelerator to provide signed and

unsigned multiplication functions. See the “Sensory Speech 7 Technology Library Manual” for information on these

macros and their application.

The L1/Multiplier unit may be independently powered down by programming the register D6.Bit 4 to “0” (“clkExt”

Digital Filter

The RSC-4128 has a Digital Filter engine capable of dividing up a frequency range into several smaller ranges. It

is also capable of reporting characteristics of each range to the RSC-4128 processor. The configuration of the

Digital Filter engine and access to signal characteristics generated are enabled by technology modules which are

available from Sensory “Technology Support” upon request.

Power and Wakeup Control

The typical Active Supply Current is realized when operating with a main clock rate of 14.32 MHz at 3V and all I/O

configured to the high-Z state. Lowering clock frequency reduces active power consumption, although Sensory

Speech 7 technology typically requires a 14.32 MHz clock.

Two supply current power-down modes are available – Sleep and Idle modes. In Sleep mode everything is

stopped, and only an I/O event can initiate a wake-up. In Idle mode OSC2 and Timer2 continue to run, and an

Audio Wakeup, I/O Wakeup or Timer2 interrupt request caused by overflow can generate a wake-up.

Sleep mode is entered by setting register E8.Bit7=1 (“ckCtl” register; “pdn” bit), register E8.Bit0=1 (“osc1_off”) and

and register E8.Bit0=1. Setting register E8.Bit7=1 (“pdn”) freezes the processor, but does not insure that the DAC,

Audio Wakeup, and the PWM are placed in the lowest possible current-consumption state. Software control must

power these blocks down prior to setting “pdn” to “1”, according to the procedures indicated in “DAC”, “Audio

Wakeup”, and “Pulse Width Modulator Analog Output” Sections. The “Sensory Speech 7 Technology Library

Manual” provides sample code for achieving the lowest current-consumption state for Sleep and Idle modes. The

state of “pdn” bit may be observed externally on the PDN pin (see pin definitions in “Package Options” section) and

used to control power down of circuitry external to the RSC-4128, if desired.

NOTE: GPIO (Ports 0,1 & 2) should be put in input mode and a known state (e.g. light pull-up) whenever possible

to conserve power, and especially in powerdown mode to achieve the specified minimum supply current

consumption. The external memory interface (A[19:0], D[7:0], -RDR, -WRC, -RDF and –WRD) automatically goes

into a high-Z state and is pulled up by a 100 Kohm internal resistor when the “pdn” bit is set, to conserve current.

whether the 14.32 clock (“fast clock”) or the 32KHz clock (“slow clock”) will be used at wakeup time, independent of

what clock rate was being used before or during power down mode. This allows the processor clock after wakeup

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