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SC2616 Datasheet(PDF) 15 Page - Semtech Corporation

Part # SC2616
Description  Complete DDR Power Solution
PDF  17 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC2616 Datasheet(HTML) 15 Page - Semtech Corporation

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 2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC2616
Description
The MLP18 is a leadless package whose electrical
connections are made by lands on the bottom surface
of the component. These lands are soldered directly to
the PC board. The MLP has an exposed die attach pad,
which enhances the thermal and electrical characteristics
enabling high power applications. Power handling capability
of the MLP package is typically >2x the power of other
common SMT packages, such as the TSSOP and SOIC
packages. In order to take full advantage of this feature
the exposed pad must be physically connected to the
PCB substrate with solder.
Thermal Pad Via Design
Thermal data for the MLP18 is based on a 4 layer PCB
incorporating vias which act as the thermal path to other
layers. (Ref: Jedec Specification JESD 51-5). Based on
thermal performance, four-layer PCB’s with vias are
recommended to effectively remove heat from the device.
Vias should be 0.3mm diameter on a 1.2mm pitch, and
should be plugged to prevent voids being formed between
the exposed pad and PCB thermal pad due to solder
escaping by capillary action. Plugging can be accomplished
by “tenting” the via during the solder mask process. The
via solder mask diameter should be 100µm larger than
the via diameter.
Mounting Considerations
Two layer boards have less copper and thus typically
require an increase in the PC board area for effective
heatsinking. The copper area immdiately surrounding
the thermal pad connection must not be interupted by
routing traces.
Exposed Pad Stencil Design
It is good practice to minimize the presence of voids within
the exposed pad inter-connection. Total elimination is
difficult but the design of the exposed pad stencil is
important, a single slotted rectangular pattern is
recommended. (If large exposed pads are screened with
excessive solder, the device may “float”, thus causing a
gap between the MLP terminal and the PCB land
metalization.) The proposed stencil designs enables out-
gassing of the solder paste during reflow as well as
controlling the finished solder thickness.



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