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TUSB5052 Datasheet(PDF) 79 Page - Texas Instruments |
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TUSB5052 Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 84 page  11–1 11 Electrical Specifications 11.1 Absolute Maximum Rating Supply voltage, VCC –0.5 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI –0.5 to VCC + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage, VO –0.5 to VCC + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Commercial Operating Condition (3.3 V) PARAMETER MIN NOM MAX UNIT VCC Supply voltage 3 3.3 3.6 V VI Input voltage 0 VCC V V High level input voltage TTL 2 VCC V VIH High level input voltage CMOS 0.7 × VCC VCC V V Low level input voltage TTL 0 0.8 V VIL Low level input voltage CMOS 0 0.2 × VCC V TA Operating temperature 0 70 °C 11.3 Electrical Characteristics, TA = 25°C, VCC 3.3 V ±5%, VSS = 0 V PARAMETER TEST CONDITIONS MIN NOM MAX UNIT V High level output voltage TTL I4 mA VCC – 0.5 V VOH High level output voltage CMOS IOH = –4 mA VCC – 0.5 V V Low level output voltage TTL I4 mA 0.5 V VOL Low level output voltage CMOS IOL = 4 mA 0.5 V V Positive threshold voltage TTL VV 1.8 V VIT+ Positive threshold voltage CMOS VI = VIH 0.7 × VCC V V Negative threshold voltage TTL VV 0.8 1.8 V VIT– Negative threshold voltage CMOS VI = VIH 0.2 × VCC V V Hysteresis (V V ) TTL VV 0.30 0.70 V Vhys Hysteresis (VIT+ – VIT–) CMOS VI = VIH 0.17 × VCC 0.3 × VCC V I High level input current TTL VV ±20 µA IIH High-level input current CMOS VI = VIH ±1 µA I Low level input current TTL VV ±20 A IIL Low-level input current CMOS VI = VIL ±1 µA IOZ Output leakage current (Hi-Z) VI = VCC or VSS ±20 µA IOL Output low drive current 0.1 mA IOH Output high drive current 0.1 mA Clock duty cycle† 50% Jitter specification† ±100 ppm CI Input capacitance 18 pF CO Output capacitance 10 pF † Applies to all clock outputs |
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