LTC2605IGN datasheet(4/16 Pages) LINER

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LTC2605/LTC2615/LTC2625

2605f

TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9)

Note 1: Absolute maximum ratings are those values beyond which the life

of a device may be impaired.

Note 2: Linearity and monotonicity are defined from code kL to code

2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),

rounded to the nearest whole code. For VREF = 4.096V and N = 16,

kL = 256 and linearity is defined from code 256 to code 65,535.

Note 3: SDA, SCL at 0V or VCC, CA0, CA1 and CA2 floating.

Note 4: Inferred from measurement at code 256 (LTC2605/LTC2605-1),

code 64 (LTC2615/LTC2615-1) or code 16 (LTC2625/LTC2625-1) and

at full scale.

Note 5: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k

Ω in parallel with 200pF to GND.

Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half

scale and half scale – 1. Load is 2k

Ω in parallel with 200pF to GND.

Note 7: CB = capacitance of one bus line in pF.

Note 8: All values refer to VIH(MIN) and VIL(MAX) levels.

Note 9: These specifications apply to LTC2605/LTC2605-1, LTC2615/

LTC2615-1 and LTC2625/LTC2625-1.

Note 10: DC Crosstalk is measured with VCC = 5V and VREF = 4096V, with

the measured DAC at midscale, unless otherwise noted.

Note 11: RL = 2kΩ to GND or VCC.

Note 12: Guaranteed by design and not production tested.

ELECTRICAL C

HARA TERISTICS The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,

unless otherwise noted.

LTC2625/-1

LTC2615/-1

LTC2605/-1

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

AC Performance

Settling Time (Note 5)

±0.024% (±1LSB at 12 Bits)

µs

±0.006% (±1LSB at 14 Bits)

µs

±0.0015% (±1LSB at 16 Bits)

µs

Settling Time for 1LSB Step

±0.024% (±1LSB at 12 Bits)

2.7

µs

(Note 6)

±0.006% (±1LSB at 14 Bits)

4.8

µs

±0.0015% (±1LSB at 16 Bits)

5.2

µs

Voltage Output Slew Rate

0.80

µs

Capacitive Load Driving

1000

Glitch Impulse

At Midscale Transition

nV • s

Multiplying Bandwidth

180

kHz

Output Voltage Noise Density

At f = 1kHz

120

nV/

√Hz

At f = 10kHz

100

nV/

√Hz

Output Voltage Noise

0.1Hz to 10Hz

µVP-P

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VCC = 2.7V to 5.5V

fSCL

SCL Clock Frequency

●

400

kHz

tHD(STA)

Hold Time (Repeated) Start Condition

●

0.6

µs

tLOW

Low Period of the SCL Clock Pin

●

1.3

µs

tHIGH

High Period of the SCL Clock Pin

●

0.6

µs

tSU(STA)

Set-Up Time for a Repeated Start Program

●

0.6

µs

tHD(DAT)

Data Hold Time

●

0.9

µs

tSU(DAT)

Data Set-Up Time

●

100

Rise Time of Both SDA and SCL Signals

(Note 7)

● 20 + 0.1CB

300

Fall Time of Both SDA and SCL Signals

(Note 7)

● 20 + 0.1CB

300

tSU(STO)

Set-Up Time for Stop Condition

●

0.6

µs

tBUF

Bus Free Time Between a Stop and Start Condition

●

1.3

µs

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