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CS42516 Datasheet(PDF) 51 Page - Cirrus Logic |
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CS42516 Datasheet(HTML) 51 Page - Cirrus Logic |
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51 / 90 page ![]() DS583F1 51 CS42516 6.5.4 SAI RIGHT-JUSTIFIED BITS (SAI_RJ16) Default = 0 Function: This bit determines how many bits to use during right-justified mode for the Serial Audio Interface Port. By default the receiver will be in RJ24 bits but can be set to RJ16 bits. 0 - 24 bit mode. 1 - 16 bit mode. 6.5.5 CODEC RIGHT-JUSTIFIED BITS (CODEC_RJ16) Default = 0 Function: This bit determines how many bits to use during Right-Justified Mode for the DAC and ADC within the CODEC Serial Port. By default, the DAC and ADC will be in RJ24 bits, but can be set to RJ16 bits. 0 - 24 bit mode. 1 - 16 bit mode. 6.6 Misc Control (address 05h) 6.6.1 EXTERNAL ADC SCLK SELECT (EXT ADC SCLK) Default = 0 Function: This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using One-Line Mode of operation. 0 - SAI_SCLK is used as external ADC SCLK. 1 - CX_SCLK is used as external ADC SCLK. 6.6.2 RMCK HIGH IMPEDANCE (HIZ_RMCK) Default = 0 Function: This bit is used to create a high-impedance output on RMCK when the clock signal is not required. 7 6 5 432 10 Ext ADC SCLK HiZ_RMCK Reserved FREEZE FILT_SEL HPF_FREEZE CODEC_SP M/S SAI_SP M/S |
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