HT46R65 datasheet(27/48 Pages) HOLTEK

27 / 48 page

HT46R65/HT46C65

Rev. 1.80

July 14, 2005

Low Voltage Reset/Detector Functions

There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These

two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to

enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is

disabled.

The RTCC register definitions are listed below.

Bit No.

Label

Function

0~2

RT0~RT2

8 to 1 multiplexer control inputs to select the real clock prescaler output

LVDC

LVD enable/disable (1/0)

QOSC

32768Hz OSC quick start-up oscillating

0/1: quickly/slowly start

LVDO

LVD detection output (1/0)

1: low voltage detected, read only

6, 7

Unused bit, read as

²0²

RTCC (09H) Register

The LVR has the same effect or function with the exter-

nal RES signal which performs chip reset. During HALT

state, both LVR and LVD are disabled.

The microcontroller provides low voltage reset circuit in

order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

0.9V~VLVR, such as changing a battery, the LVR will au-

tomatically reset the device internally.

The LVR includes the following specifications:

· The low voltage (0.9V~V

LVR) has to remain in their

original state to exceed 1ms. If the low voltage state

does not exceed 1ms, the LVR will ignore it and do not

perform a reset function.

· The LVR uses the

²OR² function with the external RES

signal to perform chip reset.

The relationship between VDD and VLVR is shown below.

Note: VOPR is the voltage range for proper chip

operation at 4MHz system clock.

5 . 5 V

3 . 0 V

2 . 2 V

0 . 9 V

V D D

V O P R

V L V R

5 . 5 V

V D D

5 . 5 V

V L V R

0 . 9 V

0 V

R e s e t S i g n a l

R e s e t

* 1

* 2

N o r m a l O p e r a t i o n

R e s e t

L V R D e t e c t V o l t a g e

Low Voltage Reset

Note:

*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system

clock pulses before entering the normal operation.

*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,

the device enters the reset mode.

HT46R65 Datasheet(PDF) 27 Page - Holtek Semiconductor Inc

HT46R65 Datasheet(HTML) 27 Page - Holtek Semiconductor Inc

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