LD7576GS datasheet(12/22 Pages) LEADTREND

12 / 22 page

LD7576/76H/76J/76K

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7576-DS-04a

December 2009

thermal treatment, component sizes and transformer

design.

Internal Slope Compensation

A fundamental issue of current mode control is the

stability problem when its duty-cycle is more than 50%. To

stabilize the control loop, slope compensation is needed

in the traditional UC384X design by injecting the ramp

signal from the RT/CT pin through a coupling capacitor. In

LD7576X series, the internal slope compensation circuit

has been implemented to simplify the external circuit

design.

On/Off Control

By pulling COMP pin lower than 1.2V will disable the gate

output pin of LD7576X series immediately. The off mode

can be released when the pull-low signal is removed.

Dual-Oscillator Green-Mode Operation

There

are

many

different

topologies

has

been

implemented in different chips for the green-mode or

power saving requirements such as “burst-mode control”,

“skipping-cycle mode”, “variable off-time control “…etc.

The basic operation theory of all these approaches

intended to reduce the switching cycles under light-load or

no-load condition either by skipping some switching

pulses or reduce the switching frequency.

By using LD proprietary dual-oscillator technique, the

green-mode frequency can be well controlled to avoid the

generation of audible noise.

Over

Load

Protection

(OLP)

Auto

Recovery

To protect the circuit from being damaged during over

load condition and short or open loop condition, the

LD7576X series is implemented with smart OLP function.

LD7576/76J

features

auto

recovery

function,

the

waveform of which is exemplified in figure 17. In the

example of the fault condition, the feedback system tends

to force the voltage loop toward the saturation and then

pull the voltage high on COMP pin (VCOMP).

When the

VCOMP ramps up to the OLP threshold of 5V and stays for

more than OLP delay time, the protection will be activated

to turn off the gate output and stop the switching of power

circuit. The OLP delay time, set by the capacitor

connected to CT pin, is to prevent the false triggering from

the

power-on

and

turn-off

transient.

The

higher

capacitance of the capacitor in CT pin, the longer OLP

delay time will be. The recommended capacitance will be

0.1

μF for a OLP delay time around 110mS and 0.047μF

for around 55mS.

A divide-by-2 counter is implemented to reduce the

average power under OLP behavior.

Whenever OLP is

activated, the output is latched off and the divide-by-2

counter starts to count the number Vcc reaches UVLO(off).

The latch will be released when Vcc reaches the 2nd time

and then the output is recovered to switching again.

With the protection mechanism, the average input power

will be minimized, so that the component temperature and

stress can be controlled within a safe operating area.

Over Load Protection (OLP) - Latch mode

Other than LD7576/76J, the LD7576H/76K features latch

mode of smart OLP. Figure 18 shows the waveform under

a fault condition when OLP is triggered. As shown in Fig.

18, the feedback system forces the voltage loop toward

the saturation and thus pulls the voltage high on COMP

pin (VCOMP). When the VCOMP ramps up to the OLP

threshold of 5.0V and stays for longer than OLP delay

time, the protection is activated and then latches off the

gate output to stop switching of the power circuit. The

delay time is to prevent the false-triggering from power-on,

turn-off transient and peak load condition. As soon as the

over load condition is removed, the controller will be kept

latched until the Vcc drops lower than 8V. It is necessary

to start another AC power-on recycling to get the output

back.

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