CY62256

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5

Switching Characteristics

Over the Operating Range

[7]

Cy62256-55

CY62256-70

Parameter

Description

Min.

Max.

Min.

Max.

Unit

Read Cycle

Read Cycle Time

55

70

ns

Address to Data Valid

55

70

ns

Data Hold from Address Change

5

5

ns

LOW to Data valid

55

70

ns

LOW to Data valid

25

35

ns

LOW to Low-Z

[8]

5

5

ns

HIGH to High-Z

[8,9]

20

25

ns

LOW to LOW-Z

[8]

5

5

ns

LOW to LOW-Z

[8,9]

20

25

ns

LOW to Power-up

0

0

ns

HIGH to Power-down

55

70

ns

Write Cycle

[10,11]

Write Cycle Time

55

70

ns

LOW to Write End

45

60

ns

Address Set-up to Write End

45

60

ns

Address Hold from Write End

0

0

ns

Address Set-up to Write Start

0

0

ns

Pulse Width

40

50

ns

Data Set-up to write End

25

30

ns

Data Hold from Write End

0

0

ns

LOW to High-Z

[8,9]

20

25

ns

HIGH to Low-Z

[8]

5

5

ns

Switching Waveforms

Read Cycle NO. 1

[12.13]

Notes:

7.Test conditions assume signal transition time of 5 ns or less, timing reference level is of 1.5V, input pulse levels of 0 to 3V, and output

voltage.

10.The internal Write time of the memory is defined by the overlap of

LOW and

LOW. Both signals must be Low to initiate a

Write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising

edge of the signal that terminates the Write.

12.Device is continuously selected.

,

13.

is HIGH for Read cycle.