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CY62256 Datasheet(PDF) 1 Page - ARTSCHIP ELECTRONICS CO.,LMITED. |
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CY62256 Datasheet(HTML) 1 Page - ARTSCHIP ELECTRONICS CO.,LMITED. |
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1 / 12 page  CY62256 www.artschip.com 1 256K (32K x 8) Static RAM Features Temperature Ranges -Commercial:0 ℃ to 70℃ -Industrial: -40 ℃ to 85℃ -Automotive: -40 ℃ to 125℃ High speed: 55ns and 70 ns Voltage range : 4.5V –5.5V operation Low active power (70ns, LL version, Com’l and Ind’l) -275mW (max) Low standby power (70ns,LL Version, Com’l and Ind’l) -28 µW (max.) Easy memory expansion with and features TTL – compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mial 28-lead PDIP packages. Functional Description [1] The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW output enable ( ) and active LOW output enable ( ) and three-state drives. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active Low write enable signal ( ) controls the writing/reading operation of the memory. When and inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, and active LOW while remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable ( ) is HIGH. Logic Block Diagram |
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