ISD9130CFI datasheet(3/415 Pages) NUVOTON

3 / 415 page

ISD9160 Technical Reference Manual

Release Date: Mar 30, 2016

- 3 -

Revision V1.41

5.7.5

PWM Double Buffering, Auto-reload and One-shot Operation .....................................156

5.7.6

Modulate Duty Cycle ....................................................................................................156

5.7.7

Dead-Zone Generator ..................................................................................................157

5.7.8

Capture Timer Operation..............................................................................................158

5.7.9

PWM-Timer Interrupt Architecture ................................................................................159

5.7.10

PWM-Timer Initialization Procedure ...........................................................................159

5.7.11

PWM-Timer Stop Procedure ......................................................................................159

5.7.12

Capture Start Procedure.............................................................................................160

5.7.13

Register Map ..............................................................................................................161

5.7.14

Register Description ...................................................................................................162

5.8

Real Time Clock (RTC) ............................................................................................ 177

5.8.1

Overview ......................................................................................................................177

5.8.2

RTC Features ...............................................................................................................177

5.8.3

RTC Block Diagram......................................................................................................178

5.8.4

RTC Function Description ............................................................................................179

5.8.5

Register Map ................................................................................................................181

5.8.6

Register Description .....................................................................................................182

5.9

Serial Peripheral Interface (SPI) Controller.............................................................. 195

5.9.1

Overview ......................................................................................................................195

5.9.2

Features .......................................................................................................................195

5.9.3

SPI Block Diagram .......................................................................................................195

5.9.4

SPI Function Descriptions ............................................................................................196

5.9.5

SPI Timing Diagram .....................................................................................................204

5.9.6

SPI Configuration Examples.........................................................................................207

5.9.7

SPI Serial Interface Control Register Map....................................................................209

5.9.8

SPI Control Register Description ..................................................................................210

5.10

Timer Controller........................................................................................................ 219

5.10.1

General Timer Controller ............................................................................................219

5.10.2

Features .....................................................................................................................219

5.10.3

Timer Controller Block Diagram..................................................................................220

5.10.4

Timer Controller Register Map ...................................................................................221

5.11

Watchdog Timer ....................................................................................................... 227

5.11.1

Watchdog Timer Control Registers Map.....................................................................229

5.12

UART Interface Controller ........................................................................................ 232

5.12.1

Overview ....................................................................................................................232

5.12.2

Features of UART controller.......................................................................................234

5.12.3

Block Diagram ............................................................................................................235

5.12.4

IrDA Mode ..................................................................................................................237

5.12.5

LIN (Local Interconnection Network) mode ................................................................239

5.12.6

UART Interface Control Register Map ........................................................................240

5.12.7

UART Interface Control Register Description .............................................................241

5.13

I2S Audio PCM Controller ........................................................................................ 262

5.13.1

Overview ....................................................................................................................262

5.13.2

Features .....................................................................................................................262

5.13.3

I2S Block Diagram......................................................................................................263

5.13.4

I2S Operation .............................................................................................................264

5.13.5

FIFO operation ...........................................................................................................265

5.13.6

I2S Control Register Map ...........................................................................................266

5.13.7

I2S Control Register Description ................................................................................267

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