4

MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series

MOTOROLA

General Parameters

General Parameters

Table 8 provides the clock AC timing specifications for the MPC7455 part numbers described herein.

Table 12 provides the L3 bus interface AC timing specifications for MSUG2 for the MPC7455 part numbers

described herein.

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Table 4.

Characteristic

Symbol

Maximum Processor Core Frequency

Unit

Notes

600 MHz

733 MHz

800 MHz

Min

Max

Min

Max

Min

Max

Processor frequency

500

600

500

733

500

800

MHz

1

VCO frequency

1000

1200

1000

1466

1000

1600

MHz

1

Notes:

1. Caution: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)

frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum

operating frequencies (see Table 4 in the MPC7455 RISC Microprocessor Hardware Specifications). Refer to the

PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4] settings.

Table 12. L3 Bus Interface AC Timing Specifications for MSUG2

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades

Unit

Notes

Min

Max

Min

Max

L3_CLK rise and

fall time

—

1.0

—

1.0

ns

1

Setup times:

Data and parity

–0.1

—

–0.1

—

ns

2, 3, 4

Input hold times:

Data and parity

,

+ 0.6

+0.6

—ns

2, 4

Valid times:

Data and parity

+ 0.4

+ 0.8

ns

5, 6, 7

Valid times:

All other outputs

—

ns

5, 7

Output hold times:

Data and parity

,

—

—

ns

5, 6, 7

Output hold times:

All other outputs

—

—

ns

5, 7

L3_CLK to high

impedance:

Data and parity

—

ns

Freescale Semiconductor, Inc.

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