MOTOROLA

MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series

5

General Parameters

L3_CLK to high

impedance:

All other outputs

—

ns

Notes:

2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage

of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 RISC Microprocessor

Hardware Specifications). Input timings are measured at the pins.

3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10 in the MPC7455

RISC Microprocessor Hardware Specifications. For consistency with other input setup time specifications, this will

be treated as negative input setup time.

an input signal that is valid for only a short time before and a short time after the midpoint between the rising and

falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.

5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling)

edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output

timings assume a purely resistive 50-

Ω load (see Figure 8 in the MPC7455 RISC Microprocessor Hardware

Specifications).

6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10 in the MPC7455 RISC

Microprocessor Hardware Specifications. For consistency with other output valid time specifications, this will be

treated as negative output valid time.

launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid

and output hold times such that the specified output signal will be valid for approximately one L3_CLK period

starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock

period after the edge it will be sampled.

8. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or

Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades

Unit

Notes

Min

Max

Min

Max

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