M50FLW080A datasheet(23/64 Pages) STMICROELECTRONICS

23 / 64 page

M50FLW080A, M50FLW080B

Bus operations

23/64

Figure 9.

LPC Bus Write waveforms (1 byte)

Table 9.

LPC Bus Write field definitions (1 byte)

Clock

Cycle

Number

Clock

Cycle

Count

Field

LAD0-

LAD3

Memory

I/O

Description

START

0000b

On the rising edge of CLK with LFRAME Low,

the contents of LAD0-LAD3 must be 0000b to

indicate the start of a LPC cycle.

CYCTYPE

+ DIR

011Xb

Indicates the type of cycle. Bits 3:2 must be

01b. Bit 1 indicates the direction of transfer: 1b

for write. Bit 0 is don’t care (X).

3-10

ADDR

XXXX

A 32-bit address is transferred, with the most

significant nibble first. A23-A31 must be set to

1. A22=1 for memory access, and A22=0 for

values for A21-A20.

11-12

DATA

XXXX

Data transfer is two cycles, starting with the

least significant nibble.

TAR

1111b

The host drives LAD0-LAD3 to 1111b to

indicate a turnaround cycle.

TAR

1111b

(float)

The LPC Flash Memory takes control of LAD0-

LAD3 during this cycle.

SYNC

0000b

The LPC Flash Memory drives LAD0-LAD3 to

0000b, indicating it has received data or a

command.

TAR

1111b

The LPC Flash Memory drives LAD0-LAD3 to

1111b, indicating a turnaround cycle.

TAR

1111b

(float)

N/A

The LPC Flash Memory floats its outputs and

the host takes control of LAD0-LAD3.

AI04430

CLK

LFRAME

LAD0-LAD3

Number of

clock cycles

START

CYCTYPE

+ DIR

ADDR

DATA

TAR

SYNC

TAR

1182212

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