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M50FLW080A Datasheet(PDF) 34 Page - STMicroelectronics |
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M50FLW080A Datasheet(HTML) 34 Page - STMicroelectronics |
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34 / 64 page  Status Register M50FLW080A, M50FLW080B 34/64 Table 14. Status Register bits Operation SR7 SR6 SR5 SR4 SR3 SR2 SR1 Program active ‘0’ X(1) 1. For Program operations during Erase Suspend, the SR6 bit is ‘1’, otherwise the SR6 bit is ‘0’. ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Program suspended ‘1 X(1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ Program completed successfully ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Program failure due to VPP Error ‘1’ X(1) ‘0’ ‘1’ ‘1’ ‘0’ ‘0’ Program failure due to Block/Sector Protection (FWH/LPC Interface only) ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘1’ Program failure due to cell failure ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase failure due to VPP Error ‘1’ ‘0’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ Erase failure due to Block/Sector Protection (FWH/LPC Interface only) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ Erase failure due to failed cell(s) in block or sector ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ |
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