TDA9112A datasheet(30/60 Pages) STMICROELECTRONICS

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TDA9112A

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Sad16h/D5 - VSyncSel

Vertical Synchronization input Selection be-

tween the one extracted from composite HV sig-

nal on pin H/HVSyn and the one on pin VSyn. No

effect if VSyncAuto bit is at 1.

0: V. sync extracted from composite signal on

H/HVSyn

pin selected

1: V. sync applied on VSyn pin selected

Sad16h/D6 - VSyncAuto

Vertical Synchronization input selection Auto-

matic mode. If enabled, the device automatically

selects between the vertical sync extracted from

composite HV signal on pin H/HVSyn and the one

on pin VSyn, based on detection mechanism. If

both are present, the one coming first is kept.

0: Disabled, selection done according to bit

VSyncSel

1: Enabled, the bit VSyncSel has no effect

Sad16h/D7 - XRayReset

Reset to 0 of XRay flag of status register effect-

ed with ACK bit of I²C-bus data transfer into reg-

ister containing the XRayReset bit. Also see de-

scription of the flag.

0: No effect

1: Reset with automatic return of the bit to 0

Sad17h/D0 - BlankMode

Blanking operation Mode.

0: Blanking pulse starting with detection of

vertical synchronization pulse and ending

with end of vertical oscillator discharge

(start of vertical sawtooth ramp on the VOut

pin)

1: Permanent blanking - high blanking level in

composite signal on pin HLckVBk is perma-

nent

Sad17h/D1 - VOutEn

Vertical Output Enable.

0: Disabled, VoffVOut on VOut pin (see Section

6.5 Vertical section

)

1: Enabled, vertical ramp with vertical position

offset on VOut pin

Sad17h/D2 - HBOutEn

Horizontal and B+ Output Enable.

0: Disabled, levels corresponding to “power

transistor off” on HOut and BOut pins (high

for HOut, high or low for BOut, depending on

BOutPol bit).

1: Enabled, horizontal deflection drive signal

on HOut pin providing that it is not inhibited

by another internal event (activated XRay

protection). B+ drive signal on BOut pin if not

inhibited by another internal event.

Programming the bit to 1 after prior value of 0,

will initiate soft start mechanism of horizontal

drive and, if this is not inhibited by another inter-

nal event, also the soft start of B+ DC/DC con-

vertor controller. See also bits BMute and BSa-

feEn.

Sad17h/D3 - BOHEdge

If the bit BOutPh is at 1, selection of Edge of Hor-

izontal drive signal to phase B+ drive Output sig-

nal on BOut pin.

1: Rising edge

0: Falling edge

If the bit BOutPh is at 0, selection of signal to

phase B+ drive output on BOut pin:

1: Horizontal frequency divided by 2 signal,

top of horizontal VCO

0: End of horizontal flyback

Sad17h/D4,D5,D6,D7 - THM, TVM, TH, TV

Test bits. They must be kept at 0 level by appli-

cation S/W.

Sad1Fh/D0 - HDCFlatEn

Enlargement of the Flat part on Horizontal Dy-

namic Correction waveform (starting at the be-

ginning of horizontal flyback).

0: Disable

1: Enable

Sad1Fh/D1 - HVDyCorPol

Polarity of HV Dynamic Correction waveform.

0: Concave (minimum in the middle of the pa-

rabola)

1: Convex (maximum in the middle of the pa-

rabola)

Sad1Fh/D2 - HLockSpeed

Response Speed of lock-to-unlock transition of

H-lock component on HLock output and HLock

I²C-bus flag at signal change.

0: Low

1: High

TDA9112A Datasheet(PDF) 30 Page - STMicroelectronics

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