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NM1482KSLAXCL Datasheet(PDF) 71 Page - Nanya Technology Corporation. |
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NM1482KSLAXCL Datasheet(HTML) 71 Page - Nanya Technology Corporation. |
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71 / 121 page ![]() Version 1.6 71 Nanya Technology Corp. 05/2018 All Rights Reserved. © 4Gb SLC NAND + 2Gb LPDDR2 NM148(F)2KSLAXCL/NM1482NSLAXCL NTC Proprietary Level: Property Auto-Program Operation with Data Cache Timing Diagram (3/3) (*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following equation. tPROG = tPROG of the last page + tPROG of the previous page − A A = (command input cycle + address input cycle + data input cycle time of the last page) If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max. NOTE : Make sure to terminate the operation with 80h-10h- command sequence. If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status Read command (70h) and make sure the previous page program operation is completed. If the page program operation is completed issue FFh reset before next operation. |
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